llvm::TargetLowering

This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

Synopsis

Declared in <llvm/CodeGen/TargetLowering.h>

class TargetLowering
    : public TargetLoweringBase

Description

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Base Classes

NameDescription
TargetLoweringBaseThis base class for TargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.

Types

NameDescription
AddrMode Describes a target addressing mode of base, offset, register, and scale components.
ArgListEntry Describes a single call argument, including its value, type, and ABI attribute flags.
AsmOperandInfo This contains information for each constraint that we are lowering.
CallLoweringInfo Holds all information necessary for lowering a call to SelectionDAG.
CondMergingParams Holds cost parameters that control whether two merged branch conditions should be split.
DAGCombinerInfo Holds context passed to target DAG-combine hooks, including the DAG and combine level.
IntrinsicInfo Holds memory-access information describing how a target intrinsic touches memory.
MakeLibCallOptions Holds options that control how a call to a runtime library function is generated.
PtrAuthInfo Holds the key and discriminator needed to lower a pointer-authenticated indirect call.
TargetLoweringOpt Holds a DAG and Old/New values for returning combine results to clients.
ValueTypeActionImpl Tracks the legalize-type action to use for each value type.

Type Aliases

NameDescription
ArgListTy A list of call arguments.
AsmOperandInfoVector A list of inline asm operand descriptors.
ConstraintGroup A prioritized list of constraint codes and their types for an operand.
ConstraintPair A pairing of a constraint code string with its constraint type.
LegalizeKind LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Enums

NameDescription
AndOrSETCCFoldKind Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)).
AtomicExpansionKind Specifies how an atomic instruction should be expanded, if at all.
BooleanContent Enum that describes how the target represents true/false values.
ConstraintType Classification of an inline-asm constraint code.
ConstraintWeight Relative preference weight for matching an inline-asm constraint.
ExtractSubvectorCost Enum that specifies how expensive lowering an EXTRACT_SUBVECTOR is.
LegalizeAction This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
LegalizeTypeAction This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.
MulExpansionKind Enum that specifies when a multiplication should be expanded.
NegatibleCost Enum that specifies when a float negation is beneficial.
ReciprocalEstimate Reciprocal estimate status values used by the functions below.
SelectSupportKind Enum that describes what type of support for selects the target has.
ShiftLegalizationStrategy Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recursion depth - how many expansion needed.

Member Functions

NameDescription
TargetLowering [constructor]Constructors
~TargetLowering [destructor] [virtual]Virtual destructor.
operator= Deleted copy-assignment operator.
AdjustInstrPostInstrSelection [virtual]Adjust an instruction after instruction selection using target-specific hooks.
BuildSDIV Build the expansion of a signed division using reciprocal multiplication.
BuildSDIVPow2 [virtual]Provide custom lowering of signed division by a power-of-2 constant.
BuildSREMPow2 [virtual]Provide custom lowering of signed remainder by a power-of-2 constant.
BuildUDIV Build the expansion of an unsigned division using reciprocal multiplication.
CTTZTableLookup Expand CTTZ via Table Lookup.
CanLowerReturn [virtual]Return true if the specified return values can fit into the target's return registers.
CollectTargetIntrinsicOperands [virtual]Collect the SelectionDAG operands for a target intrinsic call.
ComputeConstraintToUse [virtual]Determine the constraint code and constraint type to use for an inline asm operand.
ComputeNumSignBitsForTargetNode [virtual]Return the number of known sign bits for a target-specific SelectionDAG node.
EmitInstrWithCustomInserter [virtual]Expand a pseudo-instruction marked usesCustomInserter into a sequence of instructions.
EmitKCFICheck [virtual]Emit a KCFI type-check instruction before an indirect call.
HandleByVal [virtual]Target-specific cleanup for formal ByVal parameters.
IncrementMemoryAddress Increment a memory address according to the type and mask of the stored or loaded data.
InstructionOpcodeToISD Get the ISD node that corresponds to the Instruction class opcode.
IntrinsicIDToISD Get the ISD node that corresponds to the Intrinsic ID. Returns ISD::DELETED_NODE by default for an unsupported Intrinsic ID.
IsDesirableToPromoteOp [virtual]Return true if the DAG combiner should promote the specified node, and give the promotion type.
LegalizeSetCCCondCode Legalize a SETCC with given LHS and RHS and condition code CC on the current target.
LowerAsmOperandForConstraint [virtual]Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.
LowerAsmOutputForConstraint [virtual]Lower a custom inline asm output constraint into a value.
LowerCall [virtual]Lower a call into the SelectionDAG, filling in InVals with the call's return values.
LowerCallTo Lower an abstract call description into an actual call by invoking LowerCall.
LowerCustomJumpTableEntry [virtual]Lower a custom jump table entry to an MCExpr for targets with non-standard jump table encodings.
LowerFormalArguments [virtual]Lower the incoming formal arguments of a function into the SelectionDAG.
LowerOperation [virtual]Lower an operation that the target has marked for custom lowering.
LowerOperationWrapper [virtual]Custom-lower a node with an illegal operand type but legal result types.
LowerReturn [virtual]Lower the outgoing return values of a function into the SelectionDAG.
LowerToTLSEmulatedModel [virtual]Lower TLS global address SDNode for target independent emulated TLS model.
LowerXConstraint [virtual]Replace the generic 'X' inline asm constraint with a more specific one based on the operand type.
ParseConstraints [virtual]Split an inline asm constraint string into individual constraints tied to their operands.
PerformDAGCombine [virtual]This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
ReplaceNodeResults [virtual]Custom-lower a node whose result type is illegal for the target.
ShouldShrinkFPConstant [virtual]Return true if the FP constant of the given type should be shrunk to a smaller type.
ShrinkDemandedConstant Shrink a constant operand by clearing bits that are not demanded.
ShrinkDemandedOp Narrow an operation to a smaller type when the widening casts are free.
SimplifyDemandedBits Simplify Op using only its demanded bits, or compute its known bits.
SimplifyDemandedBitsForTargetNode [virtual]Simplify a target-specific node using only its demanded bits and elements.
SimplifyDemandedVectorElts Simplify a vector operation using only its demanded elements, or compute known undef/zero elements.
SimplifyDemandedVectorEltsForTargetNode [virtual]Simplify a target-specific node using only its demanded vector elements.
SimplifyMultipleUseDemandedBits SimplifyMultipleUseDemandedBits overloads
SimplifyMultipleUseDemandedBitsForTargetNode [virtual]More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.
SimplifyMultipleUseDemandedVectorElts Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all bits from only some vector elements.
SimplifySetCC Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.
addressingModeSupportsTLS [virtual]Returns true if the targets addressing mode can target thread local storage (TLS).
aggressivelyPreferBuildVectorSources [virtual]Return true if it is profitable to use a scalar input to a BUILD_VECTOR even with multiple uses.
alignLoopsWithOptSize [virtual]Should loops be aligned even when the function is marked OptSize (but not MinSize).
allowTruncateForTailCall [virtual]Return true if truncating from FromTy to ToTy is permitted for a tail call.
allowsMemoryAccess Return true if the target supports a memory access of the given type, address space, and alignment.
allowsMemoryAccessForAlignment Return true if the memory access is aligned or the target allows the given unaligned access.
allowsMisalignedMemoryAccesses allowsMisalignedMemoryAccesses overloads
annotateStackObjectPointer Annotate a stack object pointer with known-bits assertions.
areJTsAllowed [virtual]Return true if lowering to a jump table is allowed.
areTwoSDNodeTargetMMOFlagsMergeable [virtual]Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
atomicOperationOrderAfterFenceSplit [virtual]Return the memory ordering to assign to an atomic instruction after AtomicExpandPass splits out its fences.
buildLegalVectorShuffle Build a legal vector shuffle from the given operands and mask, trying equivalent variations if needed.
buildSDIVPow2WithCMov Build a signed division by a power of two using conditional-move instructions.
canCombineStoreAndExtract [virtual]Return true if the target can combine store(extractelement VectorTy, Idx). Cost[out] gives the cost of that transformation when this is true.
canCombineTruncStore [virtual]Return true if a truncating store of the given types can be combined, optionally requiring it to be legal.
canCreateUndefOrPoisonForTargetNode [virtual]Return true if Op can create undef or poison from non-undef & non-poison operands. The DemandedElts argument limits the check to the requested vector elements.
canMergeStoresTo [virtual]Returns if it's reasonable to merge stores to MemVT size.
canOpTrap [virtual]Returns true if the operation can trap for the value type.
canTransformPtrArithOutOfBounds [virtual]True if the target allows transformations of in-bounds pointer arithmetic that cause out-of-bounds intermediate results.
combineRepeatedFPDivisors [virtual]Return the minimum number of uses of a divisor needed before combining repeated FDIVs by it.
computeKnownAlignForTargetInstr [virtual]Compute the known alignment of a pointer value produced by a target GlobalISel instruction.
computeKnownBitsForStackObjectPointer [virtual]Determine known bits of a pointer to a known valid stack object. The default implementation computes low bits based on alignment.
computeKnownBitsForTargetInstr [virtual]Compute the known bits of a value produced by a target-specific GlobalISel instruction.
computeKnownBitsForTargetNode [virtual]Compute the known bits of a target-specific SelectionDAG node.
computeKnownFPClassForTargetInstr [virtual]Compute known floating-point class information for a value produced by a target GlobalISel instruction.
computeKnownFPClassForTargetNode [virtual]Compute known floating-point class information for a target-specific SelectionDAG node.
computeNumSignBitsForTargetInstr [virtual]Compute the number of known sign bits for a target-specific GlobalISel instruction.
convertSelectOfConstantsToMath [virtual]Return true if a select between two constants should be converted into simple arithmetic on the condition.
convertSetCCLogicToBitwiseLogic [virtual]Return true if pairs of comparisons should be combined using bitwise logic instead of logical ops.
createComplexDeinterleavingIR [virtual]Create the IR node for the given complex deinterleaving operation. If one cannot be created using all the given inputs, nullptr should be returned.
createFastISel [virtual]This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
createSelectForFMINNUM_FMAXNUM Convert an FMINNUM/FMAXNUM node into an equivalent compare-and-select sequence.
decomposeMulByConstant [virtual]Return true if multiplying by this constant should be decomposed into shifts and adds.
emitAtomicCmpXchgNoStoreLLBalance [virtual]Emit balancing code for the load-linked when the store-conditional of a cmpxchg will not execute.
emitBitTestAtomicRMWIntrinsic [virtual]Expand an atomicrmw into a target-specific bit-test intrinsic.
emitCmpArithAtomicRMWIntrinsic [virtual]Expand an atomicrmw whose result is only compared into a target-specific compare-and-arith intrinsic.
emitExpandAtomicCmpXchg [virtual]Perform a cmpxchg expansion using a target-specific method.
emitExpandAtomicLoad [virtual]Perform a atomic load using a target-specific way.
emitExpandAtomicRMW [virtual]Expand an atomicrmw instruction using a target-specific lowering.
emitExpandAtomicStore [virtual]Perform a atomic store using a target-specific way.
emitLeadingFence [virtual]Insert a fence before an atomic instruction, as needed for the target's memory model.
emitLoadLinked [virtual]Emit a load-linked operation on the given address for an ll/sc atomic sequence.
emitMaskedAtomicCmpXchgIntrinsic [virtual]Expand a masked cmpxchg into a target-specific ll/sc intrinsic.
emitMaskedAtomicRMWIntrinsic [virtual]Expand a masked atomicrmw into a target-specific ll/sc intrinsic.
emitStackGuardMixFP [virtual]Mix the frame pointer into the stack guard value for stack protector checks.
emitStoreConditional [virtual]Perform a store-conditional operation to Addr. Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
emitTrailingFence [virtual]Emit a trailing fence after expanding an atomic operation.
enableAggressiveFMAFusion Return true if the target always benefits from fusing multiply-add into FMA for this type.
enableExtLdPromotion Return true if extending loads should be promoted through chains of promotable instructions.
expandABD Expand ABDS/ABDU nodes. Expands vector/scalar ABDS/ABDU nodes.
expandABS Expand an ABS node into shift, xor, and add operations.
expandAVG Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes.
expandAddSubSat Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This method accepts integers as its arguments.
expandBITREVERSE Expand BITREVERSE nodes. Expands scalar/vector BITREVERSE nodes. Returns SDValue() if expand fails.
expandBSWAP Expand BSWAP nodes. Expands scalar/vector BSWAP nodes with i16/i32/i64 scalar types. Returns SDValue() if expand fails.
expandCLMUL Expand carryless multiply.
expandCMP Method for building the DAG expansion of ISD::[US]CMP. This method accepts integers as its arguments
expandCONVERT_FROM_ARBITRARY_FP Expand CONVERT_FROM_ARBITRARY_FP using bit manipulation.
expandCONVERT_TO_ARBITRARY_FP Expand CONVERT_TO_ARBITRARY_FP using bit manipulation.
expandCTLS Expand CTLS (count leading sign bits) nodes. CTLS(x) = CTLZ(OR(SHL(XOR(x, SRA(x, BW-1)), 1), 1))
expandCTLZ Expand CTLZ/CTLZ_ZERO_POISON nodes. Expands vector/scalar CTLZ nodes, vector nodes can only succeed if all operations are legal/custom.
expandCTPOP Expand CTPOP nodes. Expands vector/scalar CTPOP nodes, vector nodes can only succeed if all operations are legal/custom.
expandCTTZ Expand CTTZ/CTTZ_ZERO_POISON nodes. Expands vector/scalar CTTZ nodes, vector nodes can only succeed if all operations are legal/custom.
expandCttzElts Expand a CTTZ_ELTS or CTTZ_ELTS_ZERO_POISON by calculating (VL - i) for each active lane (i), getting the maximum and subtracting it from VL.
expandDIVREMByConstant Expand a division or remainder by a constant using a narrower-width algorithm.
expandFCANONICALIZE Expand FCANONICALIZE to FMUL with 1.
expandFMINIMUMNUM_FMAXIMUMNUM Expand fminimumnum/fmaximumnum into multiple comparison with selects.
expandFMINIMUM_FMAXIMUM Expand fminimum/fmaximum into multiple comparison with selects.
expandFMINNUM_FMAXNUM Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
expandFP_ROUND Expand round(fp) to fp conversion.
expandFP_TO_INT_SAT Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
expandFP_TO_SINT Expand float(f32) to SINT(i64) conversion
expandFP_TO_UINT Expand float to UINT conversion
expandFixedPointDiv Expand a fixed-point division or saturating division node.
expandFixedPointMul Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This method accepts integers as its arguments.
expandFunnelShift Expand funnel shift.
expandIS_FPCLASS Expand check for floating point class.
expandIndirectJTBranch [virtual]Expands target specific indirect branch for the case of JumpTable expansion.
expandIntMINMAX Method for building the DAG expansion of ISD::[US][MIN|MAX]. This method accepts integers as its arguments.
expandLoopDependenceMask Expand LOOP_DEPENDENCE_MASK nodes
expandMUL Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.
expandMULO Method for building the DAG expansion of ISD::[US]MULO. Returns whether expansion was successful and populates the Result and Overflow arguments.
expandMUL_LOHI Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.
expandMultipleResultFPLibCall Expand a node with multiple results into a call to an FP or vector libcall.
expandPDEP Expand parallel bit deposit (expand).
expandPEXT Expand parallel bit extract (compress).
expandPartialReduceMLA Expands PARTIAL_REDUCE_S/UMLA nodes to a series of simpler operations, consisting of zext/sext, extract_subvector, mul and add operations.
expandREM Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal. Returns true if the expansion was successful.
expandROT Expand rotations.
expandRoundInexactToOdd Truncate Op to ResultVT. If the result is exact, leave it alone. If it is not exact, force the result to be odd.
expandSADDSUBO Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion always suceeds and populates the Result and Overflow arguments.
expandShiftParts Expand shift-by-parts.
expandShlSat Method for building the DAG expansion of ISD::[US]SHLSAT. This method accepts integers as its arguments.
expandUADDSUBO Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion always suceeds and populates the Result and Overflow arguments.
expandUINT_TO_FP Expand UINT(i64) to double(f64) conversion
expandUnalignedLoad Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.
expandUnalignedStore Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
expandVECTOR_COMPRESS Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily, advance store position, before re-loading the final vector.
expandVPCTTZElements Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_POISON nodes.
expandVecReduce Expand a VECREDUCE_* into an explicit calculation. If Count is specified, only the first Count elements of the vector are used.
expandVecReduceSeq Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.
expandVectorFindLastActive Expand VECTOR_FIND_LAST_ACTIVE nodes
expandVectorMatch Expand VECTOR_MATCH nodes.
expandVectorNaryOpBySplitting Expand a vector n-ary operation by splitting it into smaller-length operations and joining the results.
expandVectorSplice Method for building the DAG expansion of ISD::VECTOR_SPLICE. This method accepts vectors as its arguments.
fallBackToDAGISel [virtual]Return true if GlobalISel should fall back to SelectionDAG ISel for the given instruction.
finalizeLowering [virtual]Perform target-specific finalization after instruction selection, such as freezing reserved registers.
findOptimalMemOpLowering [virtual]Determine the optimal sequence of memory operations to lower a memset or memcpy.
forceExpandMultiply Expand a wide multiply by splitting the operands into pieces multiplied and added without MULH.
forceExpandWideMUL Compute the full double-width product of LHS and RHS via a libcall or brute-force expansion.
functionArgumentNeedsConsecutiveRegisters [virtual]Return true if the argument type must be passed in a block of consecutive registers.
generateFMAsInMachineCombiner [virtual]Return true if forming FMAs should be delegated to the machine combiner instead of done during selection.
getABIAlignmentForCallingConv [virtual]Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.
getAddrModeArguments [virtual]Return the address operands of an intrinsic that should be sunk into the address mode.
getAsmOperandValueType [virtual]Return the EVT to use for an inline asm operand of the given IR type.
getAtomicMemOperandFlags Return the MachineMemOperand flags to use for the given atomic instruction.
getBitWidthForCttzElements Return the minimum number of bits required to hold the maximum possible number of trailing zero vector elements.
getBooleanContents getBooleanContents overloads
getByValTypeAlignment [virtual]Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.
getBypassSlowDivWidths Returns map of slow types for division or remainder with corresponding fast types
getCheaperNegatedExpression This is the helper function to return the newly negated expression only when the cost is cheaper.
getCheaperOrNeutralNegatedExpression Return the negated form of Op if it is no more expensive than the given threshold, else an empty value.
getCmpLibcallReturnType [virtual]Return the value type used for floating-point comparison libcalls.
getCondCodeAction Return how the given condition code should be treated for comparisons of the given type.
getConstraintPreferences Return the inline asm constraint codes for an operand, sorted by preference.
getConstraintType [virtual]Given a constraint, return the type of constraint it is for this target.
getCustomCtpopCost [virtual]Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.
getCustomLoadAction [virtual]Return the custom action to use for a load when the coarse lookup yields Custom.
getCustomOperationAction [virtual]How to legalize this custom operation?
getCustomTruncStoreAction [virtual]Return the custom action to use for a truncating store when the coarse lookup yields Custom.
getDivRefinementSteps Return the number of Newton-Raphson refinement steps for a reciprocal division estimate.
getExceptionPointerRegister [virtual]If a physical register, this returns the register that receives the exception address on entry to an EH pad.
getExceptionSelectorRegister [virtual]If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
getExtendForAtomicCmpSwapArg [virtual]Return how the comparison operand of an atomic compare-and-swap should be extended.
getExtendForAtomicOps [virtual]Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
getExtendForAtomicRMWArg [virtual]Returns how the platform's atomic rmw operations expect their input argument to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
getExtractSubvectorCost [virtual]Return the cost of extracting a subvector of type ResVT from a vector of type SrcVT, starting at element Index.
getFenceOperandTy [virtual]Return the type for operands of fence. TODO: Let fence operands be of i32 type and remove this.
getFixedPointOperationAction Return how a fixed-point operation with the given scale should be treated by the target.
getFrameIndexTy Return the type for frame index, which is determined by the alloca address space specified through the data layout.
getGatherAllAliasesMaxDepth Return the maximum alias-chain search depth used by GatherAllAliases.
getIRStackGuard [virtual]Return the address of the target's standard stack protector guard, or nullptr if none.
getInboundsVectorElementPointer Get an in-bounds pointer to a vector element for a vector known to fit in memory.
getIndexedLoadAction Return how the given indexed load addressing mode should be treated for the given type.
getIndexedMaskedLoadAction Return how the given indexed masked load addressing mode should be treated for the given type.
getIndexedMaskedStoreAction Return how the given indexed masked store addressing mode should be treated for the given type.
getIndexedStoreAction Return how the given indexed store addressing mode should be treated for the given type.
getInlineAsmMemConstraint [virtual]Map an inline asm memory constraint code string to its ConstraintCode enum value.
getJumpConditionMergingParams [virtual]Return the cost parameters used to decide whether to keep two branch conditions merged.
getJumpTableEncoding [virtual]Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
getJumpTableRegTy [virtual]Return the register type to use for jump table targets.
getLegalTypeToTransformTo Perform getTypeToTransformTo repeatedly until a legal type is obtained. Useful for vector operations that might take multiple steps to legalize.
getLibcallCallingConv Get the CallingConv that should be used for the specified libcall. Return the libcall Calling Conv.
getLibcallImpl Get the libcall impl routine name for the specified libcall.
getLibcallImplCallingConv Get the CallingConv that should be used for the specified libcall implementation.
getLibcallLoweringInfo Return the libcall lowering info for this target.
getLibcallName Return the libcall routine name for the specified libcall.
getLoadAction Return how a load with the given extension type should be treated for the given types.
getLoadMemOperandFlags Return the MachineMemOperand flags to use for the given load instruction.
getMaxAtomicSizeInBitsSupported Return the maximum atomic operation size in bits supported by the backend.
getMaxDivRemBitWidthSupported Returns the size in bits of the maximum div/rem the backend supports. Larger operations will be expanded by ExpandIRInsts.
getMaxExpandSizeMemcmp Get maximum # of load operations permitted for memcmp
getMaxGluedStoresPerMemcpy [virtual]Get maximum # of store operations to be glued together
getMaxLargeFPConvertBitWidthSupported Returns the size in bits of the maximum fp to/from int conversion the backend supports. Larger operations will be expanded by ExpandIRInsts.
getMaxPermittedBytesForAlignment [virtual]Return the maximum amount of bytes allowed to be emitted when padding for alignment
getMaxStoresPerMemcpy Get maximum # of store operations permitted for llvm.memcpy
getMaxStoresPerMemmove Get maximum # of store operations permitted for llvm.memmove
getMaxStoresPerMemset Get maximum # of store operations permitted for llvm.memset
getMaxSupportedInterleaveFactor [virtual]Get the maximum supported factor for interleaved memory accesses. Default to be the minimum interleave factor: 2.
getMaximumJumpTableSize Return upper limit for number of entries in a jump table. Zero if no limit.
getMaximumLegalStoreInBits Return maximum known-legal store size, which can be guaranteed for scalable vectors.
getMemValueType Return the in-memory EVT corresponding to the given LLVM IR type.
getMemcpyImpl Return the libcall implementation to use for memcpy.
getMinCmpXchgSizeInBits Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. Any smaller operations are widened in AtomicExpandPass.
getMinFunctionAlignment Return the minimum function alignment.
getMinStackArgumentAlignment Return the minimum stack alignment of an argument.
getMinimumBitTestCmps Retuen the minimum of largest number of comparisons in BitTest.
getMinimumJumpTableDensity Return lower limit of the density in a jump table.
getMinimumJumpTableEntries [virtual]Return lower limit for number of blocks in a jump table.
getMultipleConstraintMatchWeight [virtual]Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.
getNegatedExpression getNegatedExpression overloads
getNumRegisters [virtual]Return the number of registers that this ValueType will eventually require.
getNumRegistersForCallingConv [virtual]Return the number of registers needed to pass a value of this type under the given calling convention.
getOperationAction Return how the given operation should be treated for the given value type.
getOptimalMemOpLLT [virtual]Return the optimal LLT for load/store operations when lowering mem* ops.
getOptimalMemOpType [virtual]Return the optimal type to use for load/store operations when lowering memset, memcpy, or memmove.
getPICJumpTableRelocBase [virtual]Returns relocation base for the given PIC jumptable.
getPICJumpTableRelocBaseExpr [virtual]This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
getPartialReduceMLAAction Return how a partial-reduce multiply-accumulate node with the given accumulator and input types should be treated.
getPointerMemTy [virtual]Return the in-memory pointer type for the given address space.
getPointerTy [virtual]Return the pointer type for the given address space.
getPostIndexedAddressParts [virtual]Return true and the base/offset/mode if a node can form a post-indexed load or store.
getPreIndexedAddressParts [virtual]Return true and the base/offset/mode if a node's address can be represented as a pre-indexed load or store.
getPrefFunctionAlignment Return the preferred function alignment.
getPrefLoopAlignment [virtual]Return the preferred loop alignment.
getPreferredFPToIntOpcode [virtual]Return the preferred FP-to-integer conversion opcode to use as a replacement for an illegal one.
getPreferredLargeGEPBaseOffset [virtual]Return the prefered common base offset.
getPreferredShiftAmountTy [virtual]Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
getPreferredShrunkVectorSizeInBits [virtual]Return the bit size to which a vector operation should be shrunk when only its low elements are demanded.
getPreferredSwitchConditionType [virtual]Returns preferred type for switch condition.
getPreferredVectorAction [virtual]Return the preferred vector type legalization action.
getProgramPointerTy Return the type for code pointers, which is determined by the program address space specified through the data layout.
getRecipEstimate [virtual]Return a reciprocal estimate for the input operand, or an empty value if unsupported.
getRecipEstimateDivEnabled Return whether reciprocal division estimation is enabled for the given type.
getRecipEstimateSqrtEnabled Return whether reciprocal square-root estimation is enabled for the given type.
getRegClassFor [virtual]Return the register class that should be used for the specified value type.
getRegForInlineAsmConstraint [virtual]Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.
getRegisterByName [virtual]Return the physical register corresponding to the given register name.
getRegisterType Return the type of registers that this ValueType will eventually require.
getRegisterTypeForCallingConv [virtual]Return the register type to use for a value of this type under the given calling convention.
getRepRegClassCostFor [virtual]Return the cost of the 'representative' register class for the specified value type.
getRepRegClassFor [virtual]Return the 'representative' register class for the specified value type.
getRoundingControlRegisters [virtual]Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
getRuntimeLibcallsInfo Return the runtime libcalls info for this target.
getSDagStackGuard [virtual]Return the stack guard variable previously inserted by insertSSPDeclarations.
getSSPStackGuardCheck Return the target's stack protector check function, if previously inserted.
getSafeStackPointerLocation [virtual]Returns the target-specific address of the unsafe stack pointer.
getScalarShiftAmountTy [virtual]Return the type to use for the amount operand of a scalar shift operation.
getSchedulingPreference Return the target's preferred scheduling heuristic, optionally specialized for a given node.
getScratchRegisters [virtual]Returns a 0 terminated array of registers that can be safely used as scratch registers.
getSetCCResultType [virtual]Return the ValueType of the result of SETCC operations.
getShiftAmountTy Return the type to use for the shift amount operand of a shift opcode.
getSimpleValueType Return the MVT corresponding to this LLVM type. See getValueType.
getSingleConstraintMatchWeight [virtual]Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.
getSqrtEstimate [virtual]Return a square-root or reciprocal square-root estimate for the input operand.
getSqrtInputTest [virtual]Return a target-specific test of whether the operand is suitable for a square-root estimate.
getSqrtRefinementSteps Return the number of Newton-Raphson refinement steps for a square-root estimate.
getSqrtResultForDenormInput [virtual]Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation.
getStackPointerRegisterToSaveRestore If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
getStackProbeSymbolName [virtual]Return the name of the symbol used to emit stack probes, or empty if not applicable.
getStoreMemOperandFlags Return the MachineMemOperand flags to use for the given store instruction.
getStrictFPOperationAction Return the legalization action for a strict floating-point operation using its non-strict equivalent.
getSupportedLibcallImpl Check if this is valid libcall for the current module, otherwise RTLIB::Unsupported.
getTargetConstantFromLoad [virtual]This method returns the constant pool value that will be loaded by LD. NOTE: You must check for implicit extensions of the constant by LD.
getTargetMMOFlags getTargetMMOFlags overloads
getTargetMachine Return the target machine associated with this lowering.
getTargetNodeName [virtual]This method returns the name of a target specific DAG node.
getTgtMemIntrinsic [virtual]Return the memory-access information for an intrinsic that touches memory, if any.
getTruncStoreAction Return how a truncating store should be treated for the given value and memory types.
getTypeAction Return how values of this type should be legalized: as legal, promoted, or expanded.
getTypeConversion Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.
getTypeForExtReturn [virtual]Return the type to use when zero- or sign-extending an integer return value.
getTypeToExpandTo Return the largest legal type that this type will be expanded to.
getTypeToPromoteTo If the action for this operation is to promote, this method returns the ValueType to promote to.
getTypeToTransformTo [virtual]Return the type that this type is promoted, expanded, or otherwise transformed to.
getVPExplicitVectorLengthTy [virtual]Return the type to use for the explicit vector length operand of VP nodes.
getVPIntrinsicMemOperandFlags Return the MachineMemOperand flags to use for the given vector-predicated intrinsic.
getVaListSizeInBits [virtual]Returns the size of the platform's va_list object.
getValueType Return the EVT corresponding to the given LLVM IR type.
getValueTypeActions Return the table of per-EVT legalization actions.
getVectorElementPointer Get a pointer to a vector element at the given index within a vector stored in memory.
getVectorIdxLLT Returns the type to be used for the index operand of: G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT, G_INSERT_SUBVECTOR, and G_EXTRACT_SUBVECTOR
getVectorIdxTy Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
getVectorIdxWidth [virtual]Returns the type to be used for the index operand vector operations. By default we assume it will have the same size as an address space 0 pointer.
getVectorSubVecPointer Get a pointer to a sub-vector at the given index within a vector stored in memory.
getVectorTypeBreakdown Return the number of registers and intermediate type needed to break a vector type into legal parts.
getVectorTypeBreakdownForCallingConv [virtual]Return the register breakdown of a vector type under the given calling convention.
hasAndNot [virtual]Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
hasAndNotCompare [virtual]Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) != Y ---> (~X & Y) != 0
hasBigEndianPartOrdering Return true if the high part comes first when splitting a value of this type into parts.
hasBitTest [virtual]Return true if the target has a bit-test instruction for testing a single bit of X selected by Y.
hasExtractBitsInsn Return true if the target has BitExtract instructions.
hasFastEqualityCompare [virtual]Return the preferred type for an efficient equality comparison of integers with the given bit width.
hasInlineStackProbe [virtual]Return true if the target emits inline stack probes instead of calling a probe function.
hasMultipleConditionRegisters [virtual]Return true if the target has multiple condition registers that can hold comparison results.
hasPairedLoad [virtual]Return true if the target can combine two adjacent loads into a single paired load.
hasStackProbeSymbol [virtual]Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
hasStandaloneRem [virtual]Return true if the target can handle a standalone remainder operation.
hasTargetDAGCombine If true, the target has custom DAG combine transformations that it can perform for the specified node.
hasVectorBlend [virtual]Return true if the target has a vector blend instruction.
initializeSplitCSR [virtual]Perform necessary initialization to handle a subset of CSRs explicitly via copies. This function is called at the beginning of instruction selection.
insertCopiesSplitCSR [virtual]Insert copies of callee-saved registers in the entry and exit blocks for split-CSR handling.
insertSSPDeclarations [virtual]Inserts necessary declarations for SSP (stack protection) purpose. Should be used only when getIRStackGuard returns nullptr.
isAnyExtFree [virtual]Return true is an anyext is free from FromTy to ToTy. Usually true for scalar types when not trying to pack elements into vector lanes.
isBeneficialToExpandPowI Return true if it is beneficial to expand an llvm.powi intrinsic into multiplies.
isBinOp [virtual]Return true if the node is a math/logic binary operator.
isCheapToSpeculateCtlz [virtual]Return true if it is cheap to speculate a call to intrinsic ctlz.
isCheapToSpeculateCttz [virtual]Return true if it is cheap to speculate a call to intrinsic cttz.
isCommutativeBinOp [virtual]Returns true if the opcode is a commutative binary operation.
isComplexDeinterleavingOperationSupported [virtual]Does this target support complex deinterleaving with the given operation and type
isComplexDeinterleavingSupported [virtual]Does this target support complex deinterleaving
isCondCodeLegal Return true if the specified condition code is legal for a comparison of the specified types on this target.
isCondCodeLegalOrCustom Return true if the specified condition code is legal or custom for a comparison of the specified types on this target.
isConstFalseVal Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
isConstTrueVal Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
isCtlzFast [virtual]Return true if ctlz instruction is fast.
isCtpopFast [virtual]Return true if ctpop instruction is fast.
isDesirableToCombineLogicOpOfSETCC [virtual]Return the preferred fold kind for combining a logic op of two SETCC nodes.
isDesirableToCommuteWithShift Return true if it is profitable to commute a shift by a constant with its operand.
isDesirableToCommuteXorWithShift [virtual]Return true if it is profitable to commute a XOR with a logical shift to form a shifted NOT.
isDesirableToPullExtFromShl [virtual]GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y)
isDesirableToTransformToIntegerOp [virtual]Return true if transforming a floating-point operation into an equivalent integer operation is profitable.
isEqualityCmpFoldedWithSignedCmp [virtual]Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.
isExtFree Return true if the sign, zero, or fp extension represented by this instruction is free.
isExtLoad Return true if a load and a subsequent extend can be combined into a single extending load.
isExtendedTrueVal Return if N is a True value when extended to VT.
isExtractVecEltCheap [virtual]Return true if extracting a scalar element at the given index from this vector type is cheap.
isFAbsFree [virtual]Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
isFMADLegal Return true if the operation can be combined with another to form an FMAD node.
isFMAFasterThanFMulAndFAdd Return true if an FMA is faster than a separate fmul and fadd for this type.
isFNegFree [virtual]Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
isFPExtFoldable Return true if an fpext feeding this opcode can be folded away, as for an FMA instruction.
isFPExtFree [virtual]Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).
isFPImmLegal [virtual]Return true if the target can natively materialize the given floating-point immediate.
isFreeAddrSpaceCast [virtual]Return true if casting a pointer from SrcAS to DestAS is free.
isFsqrtCheap [virtual]Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
isGAPlusOffset [virtual]Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
isGuaranteedNotToBeUndefOrPoisonForTargetNode [virtual]Return true if a target-specific node is proven to never be undef or poison.
isInTailCallPosition Return true if the given node is in tail-call position within its function.
isIndexedLoadLegal Return true if the specified indexed load is legal on this target.
isIndexedMaskedLoadLegal Return true if the specified indexed load is legal on this target.
isIndexedMaskedStoreLegal Return true if the specified indexed load is legal on this target.
isIndexedStoreLegal Return true if the specified indexed load is legal on this target.
isIndexingLegal [virtual]Return true if the given base and offset form a legal indexed addressing mode for this instruction.
isInlineAsmTargetBranch [virtual]Return true if the given inline asm operand is a call or jump target needing address-constraint handling.
isIntDivCheap [virtual]Return true if integer division is cheaper than an equivalent sequence of shifts, adds, and multiplies.
isJumpExpensive Return true if Flow Control is an expensive operation that should be avoided.
isJumpTableRelative [virtual]Return true if jump table entries are relative to the table's address.
isKnownNeverNaNForTargetNode [virtual]If SNaN is false,
isLegalAddImmediate [virtual]Return true if the target can add this immediate to a register without materializing it.
isLegalAddScalableImmediate [virtual]Return true if the target can add this scalable immediate (multiplied by vscale) without materializing it.
isLegalAddressingMode [virtual]Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalICmpImmediate [virtual]Return true if the target can compare a register against this immediate without materializing it.
isLegalScaleForGatherScatter [virtual]Return true if the target supports scaling gather/scatter indices by the given amount.
isLegalStoreImmediate [virtual]Return true if the specified immediate is legal for the value input of a store instruction.
isLoadBitCastBeneficial [virtual]Return true if folding a bitcast into a load is beneficial for this target.
isLoadLegal Return true if the specified load with extension is legal on this target.
isLoadLegalOrCustom Return true if the specified load with extension is legal or custom on this target.
isMaskAndCmp0FoldingBeneficial [virtual]Return if the target supports combining a chain like:
isMulAddWithConstProfitable [virtual]Return true if distributing a constant multiply over a constant add is profitable.
isMultiStoresCheaperThanBitsMerge [virtual]Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
isNarrowingProfitable [virtual]Return true if it's profitable to narrow operations of type SrcVT to DestVT. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
isOffsetFoldingLegal [virtual]Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.
isOperationCustom Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
isOperationExpand Return true if the given operation must be expanded for this type.
isOperationExpandOrLibCall Return true if the given operation must be expanded or lowered to a libcall for this type.
isOperationLegal Return true if the specified operation is legal on this target.
isOperationLegalOrCustom Return true if the given operation is legal or custom for this type.
isOperationLegalOrCustomOrPromote Return true if the given operation is legal, custom, or promotable for this type.
isOperationLegalOrPromote Return true if the given operation is legal or can be made legal via promotion for this type.
isPaddedAtMostSignificantBitsWhenStored Indicates if any padding is guaranteed to go at the most significant bits when storing the type to memory and the type size isn't equal to the store size.
isPartialReduceMLALegalOrCustom Return true if a PARTIAL_REDUCE_U/SMLA node with the specified types is legal or custom for this target.
isPositionIndependent Return true if code should be generated as position-independent.
isPredictableSelectExpensive Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
isProfitableToCombineMinNumMaxNum [virtual]Return true if combining min/max-num operations is profitable for this type.
isProfitableToHoist [virtual]Return true if it is profitable to hoist the given instruction out of a loop.
isReassocProfitable Return true if reassociating an operand chain rooted at N0 with N1 is profitable.
isSDNodeAlwaysUniform [virtual]Return true if the given node's result is always uniform across threads.
isSDNodeSourceOfDivergence [virtual]Return true if the given node is a source of divergence across threads.
isSExtCheaperThanZExt [virtual]Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
isSafeMemOpType [virtual]Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
isSelectSupported [virtual]Return true if the target supports the given kind of select operation.
isShuffleMaskLegal [virtual]Return true if the given shuffle mask is legal for this vector type.
isSlowDivBypassed Returns true if target has indicated at least one type should be bypassed.
isSplatValueForTargetNode [virtual]Return true if vector Op has the same value across all DemandedElts, indicating any elements which may be undef in the output UndefElts.
isStoreBitCastBeneficial [virtual]Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
isStrictFPEnabled Return true if the target support strict float operation
isSuitableForBitTests Return true if a switch with the given case clusters is suitable for lowering to bit tests.
isSuitableForJumpTable [virtual]Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values.
isSupportedFixedPointOperation [virtual]Return true if the target natively supports the given fixed-point operation at the given scale.
isTargetCanonicalConstantNode [virtual]Returns true if the given Opc is considered a canonical constant for the target, which should not be transformed back into a BUILD_VECTOR.
isTargetCanonicalSelect [virtual]Return true if the given select node is already in the target's canonical form.
isTruncStoreLegal Return true if the specified store with truncation is legal on this target.
isTruncStoreLegalOrCustom Return true if the specified store with truncation has solution on this target.
isTruncateFree isTruncateFree overloads
isTypeDesirableForOp [virtual]Return true if using this legal type for the given opcode is desirable, not just legal.
isTypeLegal Return true if the target has native register support for the given value type.
isUsedByReturnOnly [virtual]Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call.
isVectorClearMaskLegal [virtual]Return true if the given mask can replace a vector AND with a shuffle from a constant pool.
isVectorLoadExtDesirable [virtual]Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
isXAndYEqZeroPreferableToXAndYEqY [virtual]Return true if testing X & Y against zero is preferable to testing it against Y.
isZExtFree Return true if a value of type FromTy is implicitly zero-extended to ToTy for free.
joinRegisterPartsIntoValue [virtual]Target-specific combining of register parts into its original value
lowerCmpEqZeroToCtlzSrl Lower an equality comparison against zero into a ctlz/srl pair when profitable.
lowerDeinterleaveIntrinsicToLoad [virtual]Lower a deinterleave intrinsic to a target specific load intrinsic. Return true on success. Currently only supports llvm.vector.deinterleave{2,3,5,7}
lowerEHPadEntry [virtual]Optional target hook to add target-specific actions when entering EH pad blocks. The implementation should return the resulting token chain value.
lowerIdempotentRMWIntoFencedLoad [virtual]Try to convert an idempotent atomicrmw into a fence followed by an atomic load.
lowerInterleaveIntrinsicToStore [virtual]Lower an interleave intrinsic to a target specific store intrinsic. Return true on success. Currently only supports llvm.vector.interleave{2,3,5,7}
lowerInterleavedLoad [virtual]Lower an interleaved load to target specific intrinsics. Return true on success.
lowerInterleavedStore [virtual]Lower an interleaved store to target specific intrinsics. Return true on success.
makeLibCall makeLibCall overloads
markLibCallAttributes [virtual]Attach target-specific attributes to the arguments of a libcall.
mayBeEmittedAsTailCall [virtual]Return true if the given call may be emitted as a tail call by the target.
mergeStoresAfterLegalization [virtual]Return true if stores of this type may be merged even after legalization.
needsFixedCatchObjects [virtual]Return true if the target requires catch objects to be allocated at fixed stack offsets.
optimizeExtendOrTruncateConversion [virtual]Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.
optimizeFMulOrFDivAsShiftAddBitcast [virtual]Return true if transforming a float multiply/divide by a power of two into a bitcast add/sub is desirable.
parametersInCSRMatch Return true if arguments passed in callee-saved registers match those of the calling function.
preferABDSToABSWithNSW [virtual]Return true if folding abs(sub nsw x, y) into an absolute-difference op is preferred.
preferIncOfAddToSubOfNot [virtual]These two forms are equivalent: sub %y, (xor %x, -1) add (add %x, 1), %y The variant with two add's is IR-canonical. Some targets may prefer one to the other.
preferScalarizeSplat [virtual]Return true if scalarizing an operation on a splat vector is preferred.
preferSelectsOverBooleanArithmetic [virtual]Should we prefer selects to doing arithmetic on boolean types
preferSextInRegOfTruncate [virtual]Return true if hoisting a sign-extend-in-reg before a truncate is preferred.
preferVectorizedNonPowerOfTwoTypeBreakdown [virtual]Return true if fixed-length, non-power-of-two vectors should be broken down into legal vector parts instead of scalars for internal values.
preferZeroCompareBranch [virtual]Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
preferedOpcodeForCmpEqPiecesOfOperand [virtual]Return the preferred shift or rotate opcode for comparing pieces of an operand for equality.
preferredShiftLegalizationStrategy [virtual]Return the preferred strategy for legalizing an oversized shift instruction.
prepareVolatileOrAtomicLoad [virtual]This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.
promoteTargetBoolean Promote a target boolean value to the boolean representation of the given type.
rangeFitsInWord Check whether the range [Low,High]fits in a machine word.
reduceSelectOfFPConstantLoads [virtual]Return true if converting a select of FP constants to a conditional constant-pool load is profitable.
requiresUniformRegister [virtual]Return true if the given value requires a uniform register class across divergent control flow.
scalarizeExtractedVectorLoad Replace an extraction of a load with a narrowed load.
scalarizeVectorLoad Turn load of vector type into a load of the individual elements.
scalarizeVectorStore Turn a store of a vector type into stores of its individual elements.
setLibcallImpl Set the libcall implementation to use for the given libcall.
shallExtractConstSplatVectorElementToStore [virtual]Return true if a constant vector splat should be stored by extracting a single element.
shouldAlignPointerArgs [virtual]Return true if pointer arguments to this call should be aligned by aligning the pointee object.
shouldAvoidTransformToShift [virtual]Return true if creating a shift of the type by the given amount is not profitable.
shouldCastAtomicLoadInIR [virtual]Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
shouldCastAtomicRMWIInIR [virtual]Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
shouldCastAtomicStoreInIR [virtual]Return how an atomic store should be cast by the IR-level AtomicExpand pass.
shouldConsiderGEPOffsetSplit [virtual]Return true if CodeGenPrepare should consider splitting a large GEP offset to fit the addressing mode.
shouldConvertConstantLoadToIntImm [virtual]Return true if replacing a load of this constant with an immediate is beneficial.
shouldConvertFpToSat [virtual]Return true if a saturating fp-to-int conversion should be generated for the given types.
shouldConvertPhiType [virtual]Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.
shouldConvertSplatType [virtual]Return a more profitable scalar type to use for a vector splat, or nullptr if none.
shouldExpandAtomicCmpXchgInIR [virtual]Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
shouldExpandAtomicLoadInIR [virtual]Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
shouldExpandAtomicRMWInIR [virtual]Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. Default is to never expand.
shouldExpandAtomicStoreInIR [virtual]Return how an atomic store should be expanded by the IR-level AtomicExpand pass.
shouldExpandBuildVectorWithShuffles [virtual]Return true if BUILD_VECTOR should be expanded using shuffles rather than a stack store/load.
shouldExpandGetActiveLaneMask [virtual]Return true if the llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.
shouldExpandGetVectorLength [virtual]Return true if the get.vector.length intrinsic should be expanded using generic code.
shouldExtendGSIndex [virtual]Returns true if the index type for a masked gather/scatter requires extending
shouldExtendTypeInLibCall [virtual]Returns true if arguments should be extended in lib calls.
shouldFoldConstantShiftPairToMask [virtual]Return true if folding a pair of constant shifts into a mask is profitable.
shouldFoldMaskToVariableShiftPair [virtual]Return true if clearing extreme bits with two variable shifts is preferred over masking.
shouldFoldSelectWithIdentityConstant [virtual]Return true if folding a binary op into a select with an identity constant is profitable.
shouldFoldSelectWithSingleBitTest [virtual]Return true if a select on a single-bit AND test should be folded into a shift sequence.
shouldFormOverflowOp [virtual]Return true if an overflow-checked math operation should be formed for the given opcode and type.
shouldInsertFencesForAtomic [virtual]Return true if AtomicExpandPass should insert fences and relax ordering for this atomic instruction.
shouldInsertTrailingSeqCstFenceForAtomicStore [virtual]Whether AtomicExpandPass should automatically insert a seq_cst trailing fence without reducing the ordering for this atomic store. Defaults to false.
shouldIssueAtomicLoadForAtomicEmulationLoop [virtual]Return true if an atomic load should be issued for the initial value before an atomicrmw/cmpxchg emulation loop.
shouldKeepZExtForFP16Conv [virtual]Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.
shouldLocalize [virtual]Check whether or not MI needs to be moved close to its uses.
shouldMergeStoreOfLoadsOverCall [virtual]Returns true if it's profitable to allow merging store of loads when there are functions calls between the load and the store.
shouldNormalizeToSelectSequence [virtual]Return true if a select on a logical combination of conditions should be normalized to nested selects.
shouldOptimizeMulOverflowWithZeroHighBits [virtual]Return true if the multiply-with-overflow intrinsic should be optimized using known zero high bits.
shouldPreservePtrArith [virtual]Return true if pointer arithmetic semantics should be preserved for this pointer type.
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd [virtual]Return true if a shifted-constant AND pattern should be transformed by hoisting the constant out of the shift.
shouldReassociateReduction [virtual]Return true if two vector reductions combined by an operation should be reassociated into one reduction.
shouldReduceLoadWidth [virtual]Return true if narrowing a load to a smaller type is profitable.
shouldRemoveExtendFromGSIndex [virtual]Return true if an extend can be folded into the index operand of a masked gather or scatter.
shouldRemoveRedundantExtend [virtual]Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.
shouldScalarizeBinop [virtual]Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.
shouldSignExtendTypeInLibCall [virtual]Returns true if arguments should be sign-extended in lib calls.
shouldSimplifyDemandedVectorElts [virtual]Return true if the target supports simplifying demanded vector elements by converting them to undefs.
shouldSplatInsEltVarIndex [virtual]Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
shouldSplitFunctionArgumentsAsLittleEndian [virtual]Return true if split function arguments should be ordered as on a little-endian target.
shouldTransformSignedTruncationCheck [virtual]Return true if a signed-truncation-overflow check should be rewritten using shifts.
shouldUseDynamicVectorTypeBreakdown Return true if this vector type should use a dynamic, non-power-of-two register breakdown.
shouldUseStrictFP_TO_INT [virtual]Return true if a strict, canonicalizing FP-to-int conversion should be used instead of selecting after the fact.
signExtendConstant [virtual]Return true if this constant should be sign extended when promoting to a larger type.
softenSetCCOperands Soften the operands of a SETCC for targets that lack hardware floating-point comparisons.
splitValueIntoRegisterParts [virtual]Target-specific splitting of values into parts that fit a register storing a legal type
storeOfVectorConstantIsCheap [virtual]Return true if storing this vector constant directly is cheaper than storing its scalar elements.
supportKCFIBundles [virtual]Return true if the target supports kcfi operand bundles.
supportPtrAuthBundles [virtual]Return true if the target supports ptrauth operand bundles.
supportSplitCSR [virtual]Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.
supportSwiftError [virtual]Return true if the target supports swifterror attribute. It optimizes loads and stores to reading and writing a specific register.
supportsUnalignedAtomics Whether the target supports unaligned atomic operations.
targetShrinkDemandedConstant [virtual]Perform target-specific constant shrinking, overriding the generic ShrinkDemandedConstant behavior.
unwrapAddress [virtual]Unwrap a target-specific address-wrapping node for analysis purposes.
useFPRegsForHalfType [virtual]Return true if soft-promoted half values should be passed and returned as f32 in FP registers.
useLoadStackGuardNode [virtual]If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
useSoftFloat [virtual]Return true if the target should use software floating-point emulation.
useStackGuardMixFP [virtual]Return true if stack protector checks should mix the frame pointer into the guard value.
useTopologicalSorting [virtual]Return true if SelectionDAG nodes should be consistently processed in topological order.
visitMaskedLoad [virtual]Custom-lower a masked load node.
visitMaskedStore [virtual]Custom-lower a masked store node.

Static Member Functions

NameDescription
getExtendForContent Return the extension kind implied by the given boolean-content representation.
getLibcallImplName Get the libcall routine name for the specified libcall implementation

Protected Member Functions

NameDescription
AddPromotedToType Override the default promotion type for the specified operation and value type.
addBypassSlowDiv Tells the code generator which bitwidths to bypass.
addRegisterClass Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.
computeRegisterProperties Once all of the register classes are added, this allows us to compute derived properties we expose.
emitPatchPoint Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
findRepresentativeClass [virtual]Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
getDefaultSafeStackPointerLocation Return the default safe-stack pointer location.
initActions Initialize all of the actions to default values.
isExtFreeImpl [virtual]Return true if the extension represented by I is free.
isLegalRC Return true if the value types that can be represented by the specified register class are all legal.
setAtomicLoadExtAction setAtomicLoadExtAction overloads
setBooleanContents Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.
setBooleanVectorContents Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.
setCondCodeAction setCondCodeAction overloads
setHasExtractBitsInsn Set whether the target has bit-extract instructions.
setIndexedLoadAction setIndexedLoadAction overloads
setIndexedMaskedLoadAction Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.
setIndexedMaskedStoreAction Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.
setIndexedStoreAction setIndexedStoreAction overloads
setJumpIsExpensive Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.
setLoadExtAction setLoadExtAction overloads
setMaxAtomicSizeInBitsSupported Set the maximum atomic operation size, in bits, supported by the backend.
setMaxBytesForAlignment Set the maximum number of bytes allowed to be emitted for loop alignment padding.
setMaxDivRemBitWidthSupported Set the size in bits of the maximum div/rem the backend supports. Larger operations will be expanded by ExpandIRInsts.
setMaxLargeFPConvertBitWidthSupported Set the size in bits of the maximum fp to/from int conversion the backend supports. Larger operations will be expanded by ExpandIRInsts.
setMaximumJumpTableSize Indicate the maximum number of entries in jump tables. Set to zero to generate unlimited jump tables.
setMinCmpXchgSizeInBits Sets the minimum cmpxchg or ll/sc size supported by the backend.
setMinFunctionAlignment Set the target's minimum function alignment.
setMinStackArgumentAlignment Set the minimum stack alignment of an argument.
setMinimumBitTestCmps Set the minimum of largest of number of comparisons to generate BitTest.
setMinimumJumpTableEntries Indicate the minimum number of blocks to generate jump tables.
setOperationAction Set the legalization action to use for the given operation and value type.
setOperationPromotedToType setOperationPromotedToType overloads
setPartialReduceMLAAction Set the legalization action for a partial-reduce multiply-accumulate node with the given types.
setPrefFunctionAlignment Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment
setPrefLoopAlignment Set the target's preferred loop alignment.
setSchedulingPreference Specify the target scheduling preference.
setStackPointerRegisterToSaveRestore If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
setSupportsUnalignedAtomics Sets whether unaligned atomic operations are supported.
setTargetDAGCombine Register the given target-independent node types for custom DAG combining.
setTruncStoreAction Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.
setTypeIdForCallsiteInfo Record the call-site type identifier used for indirect call type checking.

Protected Data Members

NameDescription
EnableExtLdPromotion Whether extending-load promotion through chains of promotable instructions is enabled.
GatherAllAliasesMaxDepth The maximum depth to search for alias-chain dependencies when merging stores.
IsStrictFPEnabled Whether the target supports strict floating-point operations.
MaxGluedStoresPerMemcpy Specify max number of store instructions to glue in inlined memcpy.
MaxLoadsPerMemcmp Specify maximum number of load instructions per memcmp call.
MaxLoadsPerMemcmpOptSize Likewise for functions with the OptSize attribute.
MaxStoresPerMemcpy Specify maximum number of store instructions per memcpy call.
MaxStoresPerMemcpyOptSize Likewise for functions with the OptSize attribute.
MaxStoresPerMemmove Specify maximum number of store instructions per memmove call.
MaxStoresPerMemmoveOptSize Likewise for functions with the OptSize attribute.
MaxStoresPerMemset Specify maximum number of store instructions per memset call.
MaxStoresPerMemsetOptSize Likewise for functions with the OptSize attribute.
PredictableSelectIsExpensive Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Non-Member Functions

NameDescription
ComputeValueVTsCompute a sequence of EVTs for the non-aggregate parts of an LLVM IR type.
ComputeValueVTsCompute a sequence of EVTs for the non-aggregate parts of an LLVM IR type.
getICmpTrueValReturns an integer representing true, as defined by the TargetBooleanContents.
isConstFalseValReturns true if given the TargetLowering's boolean contents information, the value Val contains a false value.
isConstTrueValReturns true if given the TargetLowering's boolean contents information, the value Val contains a true value.