Physical encodings of instruction operands.
Synopsis
Declared in <llvm/Support/X86DisassemblerDecoderCommon.h>
enum OperandEncoding;
Members
Name |
Description |
|
No operand encoding. |
|
Register operand in ModR/M byte. |
|
R/M operand in ModR/M byte. |
|
R/M operand with CDisp scaling of 2. |
|
R/M operand with CDisp scaling of 4. |
|
R/M operand with CDisp scaling of 8. |
|
R/M operand with CDisp scaling of 16. |
|
R/M operand with CDisp scaling of 32. |
|
R/M operand with CDisp scaling of 64. |
|
Force SIB operand in ModR/M byte. |
|
VSIB operand in ModR/M byte. |
|
VSIB operand with CDisp scaling of 2. |
|
VSIB operand with CDisp scaling of 4. |
|
VSIB operand with CDisp scaling of 8. |
|
VSIB operand with CDisp scaling of 16. |
|
VSIB operand with CDisp scaling of 32. |
|
VSIB operand with CDisp scaling of 64. |
|
Register operand in VEX.vvvv byte. |
|
Register operand in EVEX.aaa byte. |
|
1‐byte immediate. |
|
2‐byte immediate. |
|
4‐byte immediate. |
|
8‐byte immediate. |
|
(AL..DIL, R8B..R15B) Register code added to the opcode byte. |
|
(AX..DI, R8W..R15W) Register code added to the opcode byte. |
|
(EAX..EDI, R8D..R15D) Register code added to the opcode byte. |
|
(RAX..RDI, R8..R15) Register code added to the opcode byte. |
|
Position on floating‐point stack in ModR/M byte. |
|
Immediate of operand size. |
|
Immediate of address size. |
|
Immediate for static rounding control. |
|
Register code of operand size added to the opcode byte. |
|
Condition code encoded in opcode. |
|
Condition flags encoded in EVEX.VVVV. |
|
Duplicate of another operand; ID is encoded in type. |
|
Source index; encoded in OpSize/Adsize prefix. |
|
Destination index; encoded in prefixes. |
|
Sentinel past the last operand encoding. |
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