This pass provides access to the codegen interfaces that are needed for IR‐level transformations.
Synopsis
Declared in <llvm/Analysis/TargetTransformInfo.h>
class TargetTransformInfo;Types
Name |
Description |
Cost metrics used by Loop Strength Reduction. |
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Returns options for expansion of memcmp. IsZeroCmp is |
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Describe the values an operand can take. |
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Parameters that control the loop peeling transformation. |
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Describe known properties for a set of pointers. |
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Parameters that control the generic loop unrolling transformation. |
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Describe how a vector‐predicated operation should be legalized. |
Type Aliases
Name |
Description |
Alias of |
Enums
Name |
Description |
Which addressing mode Loop Strength Reduction will try to generate. |
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The possible cache levels. |
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Represents a hint about the context in which a cast is used. |
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Some targets only support masked load/store with a constant mask. |
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The type of load/store indexing. |
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Additional information about an operand's possible values. |
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Additional properties of an operand's values. |
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Kind of extend used in a partial reduction. |
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Flags indicating the kind of support for population count. |
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Shuffle pattern used when expanding a reduction intrinsic. |
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Kind of register whose bit width is being queried. |
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The various kinds of shuffle patterns for vector queries. |
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Underlying constants for 'cost' values in this interface. |
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The kind of cost model. |
Member Functions
Name |
Description |
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Constructors |
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Destroy TargetTransformInfo. |
Move‐assign TargetTransformInfo. |
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Return true if LSR should query isLegalAddressingMode with an Instruction. |
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Return false if a |
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Return a value to be added to the inlining threshold. |
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Returns true if GEP should not be used to index into vectors for this target. |
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Determine if the target supports unaligned memory accesses. |
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Return true if the two functions have compatible attributes for inlining. |
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Return true if caller and callee agree on how |
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Return true if globals in this address space can have initializers other than |
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Return true if the target can fuse a compare and branch. |
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Return true if the target can save a compare for loop count, for example hardware loop saves a compare. |
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Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer. |
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Collect kernel launch bounds for |
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Don't restrict interleaved unrolling to small loops. |
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Enable matching of interleaved access groups. |
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Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore vectorized using masked vector loads/stores. |
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Return target options for expanding memcmp. |
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Return true if we should be enabling ordered reductions for the target. |
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Return true when scalable vectorization is preferred. |
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Should the Select Optimization pass be enabled and ran. |
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Return true if prefetching should also be done for writes. |
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Return true if the target forces scalarizing of llvm.masked.gather intrinsics. |
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Return true if the target forces scalarizing of llvm.masked.scatter intrinsics. |
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Return a mask of pointer bits preserved by an address‐space cast. |
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Return the cost of computing an address for a memory operation. |
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Return the cost of an alternating‐opcode pattern lowered as one instruction. |
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Estimate the reciprocal‐throughput cost of a math or logic instruction. |
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Calculate the cost of vector reduction intrinsics. |
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Return an assumed address space for value |
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Return the max element size in bytes for unordered‐atomic mem intrinsics. |
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Return estimated branch‐misprediction penalty in latency. |
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Return the expected cost of control‐flow instructions such as Phi or Br. |
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Return the associativity of the cache level, if available. |
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Return the size of a cache line in bytes. |
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Return the size of the cache level in bytes, if available. |
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Return the cost of Call instructions. |
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Return the cost of leaving an Alloca in the caller when not inlined. |
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Return the expected cost of cast instructions such as bitcast or trunc. |
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Return the expected cost of compare and select instructions. |
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Return the cost of keeping values of the given types alive over a call. |
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Query the target for which minimum VF epilogue vectorization should use. |
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Return the estimated number of case clusters when lowering |
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Return the cost of an extended reduction pattern. |
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Return the expected cost of a sign‐ or zero‐extended vector extract. |
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Return the expected cost of supporting the floating point operation of the specified type. |
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Returns a bitmask constructed from the target‐features or fmv‐features metadata of a function corresponding to its Arch Extensions. |
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Return the address space ID for a target's flat address space. |
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Estimate the cost of a GEP operation when lowered. |
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Return the size cost of rematerializing a GlobalValue versus a reload. |
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Return the cost of inserting or extracting a lane from the vector end. |
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Return a penalty for invoking call |
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Return the vector‐instruction inlining bonus as a percent. |
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Return the profitability multiplier used by inlining cost‐benefit analysis. |
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Return the savings multiplier used by inlining cost‐benefit analysis. |
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Return the bonus of inlining the last call to a static function. |
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TODO: This is a rather blunt instrument. Perhaps altering the costs of individual classes of instructions would be better. |
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Return the expected cost of aggregate inserts and extracts. |
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Return the size‐optimization cost of materializing the given integer. |
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Return the expected cost of materializing the given integer immediate. |
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Return the materialization cost of an immediate used by an instruction. |
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Return the materialization cost of an immediate used by an intrinsic. |
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Return the cost of an interleaved memory operation. |
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Return the cost of Intrinsic instructions. Analyses the real arguments. |
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Return the largest vector bitwidth for loads and stores in |
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Return the adjusted VF if the target cannot use |
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Return the maximum interleave factor any transform should try for this target. |
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Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call. |
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Return the maximum number of function arguments the target supports. |
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Return the maximum number of iterations to prefetch ahead. |
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Return the architectural maximum vscale, if the target specifies one. |
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Return the maximum VF for the given element width and opcode, or 0. |
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Return the cost of memory intrinsic instructions. |
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Return the expected cost of a memcpy. |
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Return the type to use in a loop expansion of a memcpy call. |
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Calculate operand types to copy |
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Return the cost of Load and Store instructions. |
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Return the cost of a min/max vector reduction. |
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Return the minimum architectural page size for the target. |
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Return the minimum stride in bytes at which software prefetching is useful. |
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Return the minimum trip count to consider vectorizing with tail‐folding. |
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Return the width of the smallest vector register type. |
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Return the minimum bit width to use for integer switch lookup table elements on this target. |
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Return the minimum VF for the given element width, or 0 if there is none. |
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Return the cost of a multiply‐accumulate reduction pattern. |
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Return how many padding bytes to add for a global array of the given size. |
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Return how many parts |
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Return the number of registers in the target‐provided register class. |
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Estimate the overhead of scalarizing operands with the given types. |
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Return a value holding the result of the given memory intrinsic. |
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Return the cost of a partial reduction from a vector to a narrower vector. |
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Get target‐customized preferences for generic loop peeling. |
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Estimate the cost of a chain of pointer operations when lowered. |
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Return hardware support for population count. |
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Return a predicated pointer and its address space for value |
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If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. |
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Return the preferred addressing mode LSR should make efforts to generate. |
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Return the shuffle pattern used to expand the given reduction intrinsic. |
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Query the target what the preferred style of tail folding is. |
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Return how many instructions before a load a prefetch should be placed. |
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Returns a bitmask constructed from the target‐features or fmv‐features metadata of a function corresponding to its FMV priority. |
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Returns the estimated number of registers required to represent |
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Return the width of the largest scalar or vector register type. |
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Return the target‐provided register class ID for the provided type. |
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Return the target‐provided register class name. |
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Return the cost of reloading a register in the given class from the stack. |
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Return the cost of spilling a register in the given class to the stack. |
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Return the cost of a replication shuffle of |
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Estimate the overhead of scalarizing an instruction. |
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Return the cost of the scaling factor used in addressing mode AM. |
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Return the cost of a shuffle of kind |
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Return the minimum vectorization factor for a store instruction. |
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Return the adjusted VF if the target cannot use |
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Return true if the intrinsic is a supported memory intrinsic. |
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Get target‐customized preferences for the generic loop unrolling transformation. The caller will initialize UP with the current target‐independent defaults. |
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Return how the target needs this vector‐predicated operation transformed. |
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Return the vscale value used to tune the cost model. |
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Get target‐specific uniformity information for a value. |
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Return the expected cost of vector Insert and Extract. |
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@{ Return true if the target supports the %evl parameter of VP intrinsics. |
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Return whether a 32‐bit branch instruction is available in Arm or Thumb. |
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Return true if branch divergence exists. |
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Return true if the target supports fault‐suppressing predicated load/store. |
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Return true if the target has a unified division‐and‐remainder operation. |
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Return true if the memory access |
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Return true if the hardware has a fast carry‐less multiplication instruction. |
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Return true if the hardware has a fast square‐root instruction. |
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Combine a target‐specific intrinsic during InstCombine. |
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Handle the invalidation of this information. |
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Return true if the given type is supported for scalable vectors. |
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Return true if |
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Return true if an FP NaN check is cheaper than comparing against 0.0. |
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Return true if auto‐vectorizing FP ops may change scalar FP semantics. |
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Query the target whether it would be profitable to convert the given loop into a hardware loop. |
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Return true if the specified indexed load for the given type is legal. |
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Return true if the specified indexed store for the given type is legal. |
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Return true if LSR cost of C1 is lower than C2. |
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Return true if |
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Return true if adding |
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Return true if the given addressing mode is legal for a load/store of |
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Return true if an alternating‐opcode pattern can be a single instruction. |
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Return true if the target supports broadcasting a load to a vector. |
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Return true if |
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Return true is the target supports interleaved access for the given vector type |
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Return true if the target supports masked compress store. |
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Return true if the target supports masked expand load. |
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Return true if the target supports masked gather. |
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Return true if the target supports masked load. |
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Return true if the target supports masked scatter. |
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Return true if the target supports masked store. |
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Return true if the target supports masked vector histograms. |
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Return true if the target supports nontemporal load. |
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Return true if the target supports nontemporal store. |
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Return true if the target supports strided load. |
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Return true if the load instruction is legal to vectorize. |
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Return true if it is legal to vectorize the given load chain. |
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Return true if it is legal to vectorize the given reduction kind. |
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Return true if the store instruction is legal to vectorize. |
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Return true if it is legal to vectorize the given store chain. |
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Test whether calls to a function lower to actual program function calls. |
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Returns true if this is an instance of a function with multiple versions. |
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Return true if casting from |
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Return true if LSR should treat the number of registers as the major cost. |
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Return true if LSR should not optimize a chain that includes |
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Return true if it is profitable to hoist instruction in the then/else to before if. |
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Return true if sinking operands of |
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Return true if the target is known to be single‐threaded. |
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Identify if the vector form of the intrinsic is overloaded at |
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Identify if the vector form of the intrinsic has a scalar operand. |
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Identify if a struct‐returning vector intrinsic is overloaded at |
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Return true if it's free to truncate a value of type Ty1 to type Ty2. |
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Return true if this type is legal. |
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Determine if an instruction with Custom uniformity can be proven uniform based on which operands are uniform. |
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Query the target whether the specified address space cast from FromAS to ToAS is valid. |
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Return true if a uniform scalar shift is much cheaper than a per‐lane one. |
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Return true if SLP should use alternate‐opcode vectorization. |
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Return true if a scalar epilogue should still be considered for vectorization. |
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Return true if equal‐cost fixed‐width vectorization is preferred. |
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Return true if reductions of |
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Return true if a predicated reduction select should stay in the loop. |
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Return true if SLP should apply the 2‐element instruction‐count check. |
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Query the target whether it would be preferred to create a tail‐folded vector loop, which can avoid the need to emit a scalar epilogue loop. |
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Return true if complex constants should stay attached to |
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Return true if target doesn't mind addresses in vectors. |
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Rewrite intrinsic |
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Return true if switches should be turned into lookup tables for the target. |
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Return true if switches should be turned into lookup tables containing this constant value for the target. |
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Return true if lookup tables should be turned into relative lookup tables. |
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Return true if address type promotion should be considered for |
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Return true if VFs that exceed register pressure should be discarded. |
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Return true if |
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Return true if LSR should drop a found solution if it's calculated to be less profitable than the baseline. |
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Return true if the reduction intrinsic should be expanded to shuffles. |
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Return true if VF should match the smallest element type to a register. |
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Return true if the target wants a prefetch in address space |
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Return true if SelectOpt should treat |
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Can be used to implement target‐specific instruction combining. |
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Can be used to implement target‐specific instruction combining. |
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Return true if vector element load/store is cheap enough to skip insert/extract. |
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Return true if the target supports scalable vectors. |
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If target supports tail call on |
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If the target supports tail calls. |
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Return true if alias analysis should be used in target‐specific transforms. |
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Return true if the input function which is cold at all call sites, should use coldcc calling convention. |
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Return true if the input function is internal, should use fastcc calling convention. |
Static Member Functions
Name |
Description |
Collect common data between two OperandValueInfo inputs. |
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Calculates a CastContextHint from |
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Get the cast opcode for an extension kind. |
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Collect properties of V used in cost analysis, e.g. OP_PowerOf2. |
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Calculates a VectorInstrContext from |
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A helper function to determine the type of reduction algorithm used for a given |
Non-Member Functions
Name |
Description |
Return the cost associated with a callsite, including parameter passing and the call/return instruction. |
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