VLIW scheduler that builds the dependence graph used for packetizing.
Synopsis
Declared in <llvm/CodeGen/DFAPacketizer.h>
class DefaultVLIWScheduler
: public ScheduleDAGInstrs
Description
Extends ScheduleDAGInstrs and overrides the schedule method to build the dependence graph.
Base Classes
Name |
Description |
A ScheduleDAG for scheduling lists of MachineInstr. |
Type Aliases
Name |
Description |
List of SUnits associated with a memory value during DAG construction. |
Enums
Name |
Description |
The direction that should be used to dump the scheduled Sequence. |
Member Functions
Name |
Description |
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Construct a VLIW scheduler for |
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Copy assignment is deleted; ScheduleDAG is passed by reference only. |
IsReachable ‐ Checks if SU is reachable from TargetSU. |
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Verifies that all SUnits were scheduled and that their state is consistent. Returns the number of scheduled SUnits. |
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Adds custom features for a visualization of the ScheduleDAG. |
Add a DAG edge to the given SU with the given predecessor dependence data. |
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DefaultVLIWScheduler takes ownership of the Mutation object. |
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Adds dependencies from region instructions to the scheduling barrier. |
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Returns an iterator to the top of the current scheduling region. |
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Builds SUnits for the current scheduling region. |
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True if an edge can be added from PredSU to SuccSU without creating a cycle. |
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Clears the DAG state (between regions). |
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Returns true if MBB scheduling regions should be handled top‐down. |
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Dumps the scheduling DAG for debugging. |
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Dumps a single scheduling unit for debugging. |
Dump the printable name of |
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Returns an iterator to the bottom of the current scheduling region. |
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Initializes DAG and scheduler state for a new scheduling region. |
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Called when the scheduler has finished scheduling the current region. |
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Allow targets to perform final scheduling actions at the level of the whole MachineFunction. By default does nothing. |
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Cleans up after scheduling in the given block. |
Fixes register kill flags that scheduling has made invalid. |
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Get the specific cluster, return nullptr for InvalidClusterId. |
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Returns the array of the clusters. |
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Returns a label for the region of code covered by the DAG. |
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Returns a label for a DAG node that points to an instruction. |
Returns the MCInstrDesc of this SUnit. Returns NULL for SDNodes without a machine opcode. |
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Returns an existing SUnit for this MI, or nullptr. |
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Resolves and cache a resolved scheduling class for an SUnit. |
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Gets the machine model for instruction scheduling. |
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Creates a new SUnit and return a ptr to it. |
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Build the dependence graph for the current scheduling region. |
Sets the direction used when dumping the scheduled sequence. |
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Whether regions with a single MI should be scheduled. |
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Prepares to perform scheduling in the given block. |
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Data Members
Name |
Description |
Special node for the region entry. |
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Special node for the region exit. |
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Machine function |
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Virtual/real register map |
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The scheduling units. |
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When true, stress‐test the scheduler. |
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Target instruction information |
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Target processor |
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Target processor register info |
Protected Types
Name |
Description |
A map from ValueType to SUList, used during DAG construction, as a means of remembering which SUs depend on which memory locations. |
Protected Type Aliases
Name |
Description |
Pairs of DBG_VALUE instructions and the instructions they follow. |
Protected Member Functions
Name |
Description |
Adds barrier‐chain edges from all SUs in |
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Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency. |
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Adds data dependencies for the physical‐register operand at |
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Adds all physical‐register dependencies for the operand at |
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Adds virtual‐register definition dependencies for the operand at |
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Adds virtual‐register use dependencies for the operand at |
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Returns true if the def register in |
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Dump |
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Returns a (possibly null) pointer to the current BatchAAResults. |
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Returns a mask for which lanes get read/written by the given (register) machine operand. |
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Creates an SUnit for each instruction in the current region. |
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Apply registered DAG mutations to the current dependence graph. |
Protected Data Members
Name |
Description |
Optional batch alias‐analysis results used while adding memory deps. |
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The block in which to insert instructions |
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Generic side‐effecting instruction that acts as a scheduling barrier. |
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True if this scheduler can safely include terminators as DAG nodes. |
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Clusters of related SUnits discovered while building the DAG. |
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Tracks the last instruction(s) in this region defining each virtual register. There may be multiple current definitions for a register with disjunct lanemasks. |
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Tracks the last instructions in this region using each virtual register. |
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Remember instruction that precedes DBG_VALUE. These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule. |
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Map from register units to SUnits that define them in the current walk. |
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Direction used when dumping the schedule. |
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First DBG_VALUE instruction preceding the scheduled region, if any. |
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Set of live physical registers for updating kill flags. |
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Frame information for the function. |
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After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. |
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Loop information for the function. |
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Number of memory operations processed while building the DAG. |
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Instructions in this region (distance(RegionBegin, RegionEnd)). |
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The beginning of the range to be scheduled. |
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The end of the range to be scheduled. |
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True if the DAG builder should remove kill flags (in preparation for rescheduling). |
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TargetSchedModel provides an interface to the machine model. |
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True if regions with a single MI should be scheduled. |
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Topo ‐ A topological ordering for SUnits which permits fast IsReachable and similar queries. |
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Whether lane masks should get tracked. |
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For an unanalyzable memory access, this Value is used in maps. |
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Map from register units to SUnits that use them in the current walk. |
Non-Member Functions
Name |
Description |
Fuse two scheduling units so they are scheduled back to back. |
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