CircularSourceMgr | The default implementation of SourceMgr. It always takes a fixed number of instructions and provides an option to loop the given sequence for a certain iterations. |
CodeEmitter | A utility class used to compute instruction encodings for a code region. |
Context | |
CriticalDependency | A critical data dependency descriptor. |
CustomBehaviour | Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren't expressed well enough within the scheduling model for mca to automatically simulate them properly. If you implement this class for your target, make sure to also implement a target specific InstrPostProcess class as well. |
CycleSegment | A sequence of cycles. |
DefaultResourceStrategy | Default resource allocation strategy used by processor resource groups and processor resources with multiple units. |
DefaultSchedulerStrategy | Default instruction selection strategy used by class Scheduler. |
DispatchStage | |
EntryStage | |
ExecuteStage | |
HWEventListener | |
HWInstructionDispatchedEvent | |
HWInstructionEvent | |
HWInstructionIssuedEvent | |
HWInstructionRetiredEvent | |
HWPressureEvent | |
HWStallEvent | |
HardwareUnit | |
InOrderIssueStage | |
IncrementalSourceMgr | An implementation of SourceMgr that allows users to add new instructions incrementally / dynamically. Note that this SourceMgr takes ownership of all mca::Instruction. |
InstRef | An InstRef contains both a SourceMgr index and Instruction pair. The index is used as a unique identifier for the instruction. MCA will make use of this index as a key throughout MCA. |
InstStreamPause | This is actually not an error but a marker to indicate that the instruction stream is paused. |
InstrBuilder | A builder class that knows how to construct Instruction objects. |
InstrDesc | An instruction descriptor |
InstrPostProcess | Class which can be overriden by targets to modify the mca::Instruction objects before the pipeline starts. A common usage of this class is to add immediate operands to certain instructions or to remove Defs/Uses from an instruction where the schedulinng model is incorrect. |
Instruction | An instruction propagated through the simulated instruction pipeline. |
InstructionBase | Base class for instructions consumed by the simulation pipeline. |
InstructionError | |
InstructionTables | |
Instrument | |
InstrumentManager | This class allows targets to optionally customize the logic that resolves scheduling class IDs. Targets can use information encoded in Instrument objects to make more informed scheduling decisions. |
LSUnit | Default Load/Store Unit (LS Unit) for simulated processors. |
LSUnitBase | Abstract base interface for LS (load/store) units in llvm-mca. |
LatencyInstrument | |
MCAOperand | A representation of an mca::Instruction operand for use in mca::CustomBehaviour. |
MicroOpQueueStage | A stage that simulates a queue of instruction opcodes. |
Pipeline | A pipeline for a specific subtarget. |
PipelineOptions | This is a convenience struct to hold the parameters necessary for creating the pre-built "default" out-of-order pipeline. |
ReadDescriptor | A register read descriptor. |
ReadState | Tracks register operand latency in cycles. |
RecycledInstErr | |
RegisterFile | Manages hardware register files, and tracks register definitions for register renaming purposes. |
ReleaseAtCycles | This class represents the number of cycles per resource (fractions of cycles). That quantity is managed here as a ratio, and accessed via the double cast-operator below. The two quantities, number of cycles and number of resources, are kept separate. This is used by the ResourcePressureView to calculate the average resource cycles per instruction/iteration. |
ResourceManager | A resource manager for processor resource units and groups. |
ResourceState | A processor resource descriptor. |
ResourceStrategy | Resource allocation strategy used by hardware scheduler resources. |
ResourceUsage | Helper used by class InstrDesc to describe how hardware resources are used. |
RetireControlUnit | This class checks on every cycle if/which instructions can be retired. Instructions are retired in program order. In the event of an instruction being retired, the pipeline that owns this RetireControlUnit (RCU) gets notified. |
RetireStage | |
Scheduler | Class Scheduler is responsible for issuing instructions to pipeline resources. |
SchedulerStrategy | |
SourceMgr | Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every instruction in the sequence. |
Stage | |
StallInfo | |
View | |
WriteDescriptor | A register write descriptor. |
WriteRef | A reference to a register write. |
WriteState | Tracks uses of a register definition (e.g. register write). |