llvm::ScheduleDAGInstrs

Synopsis

Declared in <llvm/CodeGen/ScheduleDAGInstrs.h>

class ScheduleDAGInstrs
    : public ScheduleDAG

Base Classes

Name	Description
`ScheduleDAG`

Type Aliases

Name	Description
`SUList`	A list of SUnits, used in Value2SUsMap, during DAG construction. Note: to gain speed it might be worth investigating an optimized implementation of this data structure, such as a singly linked list with a memory pool (SmallVector was tried but slow and SparseSet is not applicable).

Enums

Name	Description
`DumpDirection`	The direction that should be used to dump the scheduled Sequence.

Member Functions

Name	Description
`ScheduleDAGInstrs` [constructor]
`~ScheduleDAGInstrs` [destructor] [virtual]	Destructor
`operator=` [deleted]	Copy assignment operator
`IsReachable`	IsReachable - Checks if SU is reachable from TargetSU.
`VerifyScheduledDAG`	Verifies that all SUnits were scheduled and that their state is consistent. Returns the number of scheduled SUnits.
`addCustomGraphFeatures` [virtual]	Adds custom features for a visualization of the ScheduleDAG.
`addEdge`	Add a DAG edge to the given SU with the given predecessor dependence data.
`addSchedBarrierDeps`	Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.
`begin`	Returns an iterator to the top of the current scheduling region.
`buildSchedGraph`	Builds SUnits for the current region. If `RPTracker` is non-null, compute register pressure as a side effect. The DAG builder is an efficient place to do it because it already visits operands.
`canAddEdge`	True if an edge can be added from PredSU to SuccSU without creating a cycle.
`clearDAG`	Clears the DAG state (between regions).
`doMBBSchedRegionsTopDown` [virtual]	If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.
`dump` [virtual]
`dumpNode` [virtual]
`dumpNodeName`
`end`	Returns an iterator to the bottom of the current scheduling region.
`enterRegion` [virtual]	Initialize the DAG and common scheduler state for a new scheduling region. This does not actually create the DAG, only clears it. The scheduling driver may call BuildSchedGraph multiple times per scheduling region.
`exitRegion` [virtual]	Called when the scheduler has finished scheduling the current region.
`finalizeSchedule` [virtual]	Allow targets to perform final scheduling actions at the level of the whole MachineFunction. By default does nothing.
`finishBlock` [virtual]	Cleans up after scheduling in the given block.
`fixupKills`	Fixes register kill flags that scheduling has made invalid.
`getCluster`	Get the specific cluster, return nullptr for InvalidClusterId.
`getClusters`	Returns the array of the clusters.
`getDAGName` [virtual]	Returns a label for the region of code covered by the DAG.
`getGraphNodeLabel` [virtual]	Returns a label for a DAG node that points to an instruction.
`getInstrDesc`	Returns the MCInstrDesc of this SUnit. Returns NULL for SDNodes without a machine opcode.
`getSUnit`	Returns an existing SUnit for this MI, or nullptr.
`getSchedClass`	Resolves and cache a resolved scheduling class for an SUnit.
`getSchedModel`	Gets the machine model for instruction scheduling.
`newSUnit`	Creates a new SUnit and return a ptr to it.
`schedule` [virtual]	Orders nodes according to selected style.
`setDumpDirection`
`shouldScheduleSingleMIRegions`	Whether regions with a single MI should be scheduled.
`startBlock` [virtual]	Prepares to perform scheduling in the given block.
`viewGraph`	Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.

Data Members

Name	Description
`EntrySU`	Special node for the region entry.
`ExitSU`	Special node for the region exit.
`MF`	Machine function
`MRI`	Virtual/real register map
`SUnits`	The scheduling units.
`StressSched`
`TII`	Target instruction information
`TM`	Target processor
`TRI`	Target processor register info

Protected Types

Name	Description
`Value2SUsMap`	A map from ValueType to SUList, used during DAG construction, as a means of remembering which SUs depend on which memory locations.

Protected Type Aliases

Name
`DbgValueVector`

Protected Member Functions

Name	Description
`addBarrierChain`	Adds barrier chain edges from all SUs in map, and then clear the map. This is equivalent to insertBarrierChain(), but optimized for the common case where the new BarrierChain (a global memory object) has a higher NodeNum than all SUs in map. It is assumed BarrierChain has been set before calling this.
`addChainDependencies`	`addChainDependencies` overloads
`addChainDependency`	Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency.
`addPhysRegDataDeps`
`addPhysRegDeps`
`addVRegDefDeps`
`addVRegUseDeps`
`deadDefHasNoUse`	Returns true if the def register in `MO` has no uses.
`dumpNodeAll`
`getAAForDep`	Returns a (possibly null) pointer to the current BatchAAResults.
`getLaneMaskForMO`	Returns a mask for which lanes get read/written by the given (register) machine operand.
`initSUnits`

Protected Data Members

Name	Description
`AAForDep`
`BB`	The block in which to insert instructions
`BarrierChain`	Remember a generic side-effecting instruction as we proceed. No other SU ever gets scheduled around it (except in the special case of a huge region that gets reduced).
`CanHandleTerminators`	The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. A specialized scheduler can override TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate it has taken responsibility for scheduling the terminator correctly.
`Clusters`
`CurrentVRegDefs`	Tracks the last instruction(s) in this region defining each virtual register. There may be multiple current definitions for a register with disjunct lanemasks.
`CurrentVRegUses`	Tracks the last instructions in this region using each virtual register.
`DbgValues`	Remember instruction that precedes DBG_VALUE. These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.
`Defs`	Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.
`DumpDir`
`FirstDbgValue`
`LiveRegs`	Set of live physical registers for updating kill flags.
`MFI`
`MISUnitMap`	After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.
`MLI`
`MemOpsProcessed`
`NumRegionInstrs`	Instructions in this region (distance(RegionBegin, RegionEnd)).
`RegionBegin`	The beginning of the range to be scheduled.
`RegionEnd`	The end of the range to be scheduled.
`RemoveKillFlags`	True if the DAG builder should remove kill flags (in preparation for rescheduling).
`SchedModel`	TargetSchedModel provides an interface to the machine model.
`ScheduleSingleMIRegions`	True if regions with a single MI should be scheduled.
`Topo`	Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
`TrackLaneMasks`	Whether lane masks should get tracked.
`UnknownValue`	For an unanalyzable memory access, this Value is used in maps.
`Uses`

Non-Member Functions

Name	Description
`fuseInstructionPair`	Create an artificial edge between FirstSU and SecondSU. Make data dependencies from the FirstSU also dependent on the SecondSU to prevent them from being scheduled between the FirstSU and the SecondSU and vice-versa. Fusing more than 2 instructions is not currently supported.

Derived Classes

Name	Description
`DefaultVLIWScheduler`
`ScheduleDAGMI`	ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions according to the given MachineSchedStrategy without much extra book-keeping. This is the common functionality between PreRA and PostRA MachineScheduler.
`SwingSchedulerDAG`	This class builds the dependence graph for the instructions in a loop, and attempts to schedule the instructions using the SMS algorithm.