Provide an instruction scheduling machine model to CodeGen passes.
Synopsis
Declared in <llvm/CodeGen/TargetSchedule.h>
class TargetSchedModel;
Type Aliases
Name |
Member Functions
Name |
Description |
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Default constructor |
Compute the instruction latency based on the available machine model. |
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Compute operand latency based on the available machine model. |
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Output dependency latency of a pair of defs of the same register. |
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Compute the reciprocal throughput of the given instruction. |
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TargetInstrInfo getter. |
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Maximum number of micro‐ops that may be scheduled per cycle. |
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Multiply cycle count by this factor to normalize it relative to other resources. This is the number of resource units per cycle. |
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Number of micro‐ops that may be buffered for OOO execution. |
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Multiply number of micro‐ops by this factor to normalize it relative to other resources. |
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Return the number of issue slots required for this MI. |
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Get the number of kinds of resources for this target. |
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Get a processor resource by ID for convenience. |
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Identify the processor corresponding to the current subtarget. |
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Return the original buffer size for a processor resource. |
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Multiply the number of units consumed for a resource by this factor to normalize it relative to other resources. |
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TargetSubtargetInfo getter. |
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Return true if this machine model includes cycle‐to‐cycle itinerary data. |
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Return true if this machine model includes an instruction‐level scheduling model. |
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Return true if this machine model includes an instruction‐level scheduling model or cycle‐to‐cycle itinerary data. |
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Initialize the machine model for instruction scheduling. |
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Return true if new group must begin. |
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Return true if current group must end. |
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Return the MCSchedClassDesc for this instruction. |
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