TargetInstrInfo ‐ Interface to description of machine instruction set
Synopsis
Declared in <llvm/CodeGen/TargetInstrInfo.h>
class TargetInstrInfo
: public MCInstrInfoBase Classes
Name |
Description |
Interface to description of machine instruction set. |
Types
Name |
Description |
Represents a predicate at the MachineFunction level. The control flow a MachineBranchPredicate represents is: |
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Object returned by analyzeLoopForPipelining. Allows software pipelining implementations to query attributes of the loop being pipelined and to apply target‐specific updates to the loop once pipelining is complete. |
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A pair composed of a register and a sub‐register index. Used to give some type checking when modeling Reg:SubReg. |
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A pair composed of a pair of a register and a sub‐register index, and another sub‐register index. Used to give some type checking when modeling Reg:SubReg1, SubReg2. |
Type Aliases
Enums
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Member Functions
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Description |
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Copy constructor |
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Destructor |
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Copy assignment operator |
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If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. SkipDead should be set to false at any point that dead predicate instructions should be considered as being defined. A dead predicate instruction is one that is guaranteed to be removed after a call to PredicateInstruction. |
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. |
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. |
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Create machine specific model for scheduling. |
Initialize MCInstrInfo, called by TableGen auto‐generated routines. DO NOT USE. |
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Convert the instruction into a predicated instruction. It returns true if the operation was successful. |
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Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. This is used by the tail merging pass. |
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Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT. |
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When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency. |
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Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases: |
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Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. Returns false on success and true on failure. |
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For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed. |
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Analyze the loop code, return true if it cannot be understood. Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end. |
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Analyze loop L, which must be a single‐basic‐block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. |
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This is used by the pre‐regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference. |
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Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses. This function returns true if two MIs access different memory addresses and false otherwise. |
Return true when P Opcode1 or its inversion is equal to P Opcode2. |
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Insert a dependency‐breaking instruction before MI to eliminate an unwanted dependency on OpNum. |
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Insert an architecture‐specific instruction to clear a register. If you need to avoid sideeffects (e.g. avoid XOR on x86, which sets EFLAGS), set |
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Insert a custom frame for outlined functions. |
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Return true if the given SDNode can be copied during scheduling even if it has glue. |
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Check if it's possible and beneficial to fold the addressing computation |
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Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. |
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Returns true if the tail call can be made conditional on BranchCond. |
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Assumes the instruction is already predicated and returns true if the instruction can be predicated again. |
This method commutes the operands of the given machine instruction MI. |
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This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two‐address instruction into one or more true three‐address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two‐addressness. |
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Emit instructions to copy a pair of physical registers. |
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During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. |
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During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner. |
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Decompose the machine operand's target flags into two values ‐ the direct target flag value and any of bit flags that are applied. |
Return the default expected latency for a def based on its opcode. |
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Produce the expression describing the |
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Clones instruction or the whole instruction bundle |
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Emit a load/store instruction with the same value register as |
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This function is called for all pseudo instructions that remain after register allocation. Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed. |
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Return the increase in code size needed to predicate a contiguous run of NumInsts instructions. |
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Fix up the placeholder we may add in genAlternativeCodeSequence(). |
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Returns true iff the routine could find two commutable operands in the given machine instruction. The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. If any of the INPUT values is set to the special value 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable operand, then returns its index in the corresponding argument. If both of INPUT values are set to 'CommuteAnyOperandIndex' then method looks for 2 commutable operands. If INPUT values refer to some operands of MI, then the method simply returns true if the corresponding operands are commutable and returns false otherwise. |
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'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. If MRI‐>hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise. |
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When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. The client has to decide whether the actual replacement is beneficial or not. |
Return the machine instruction descriptor that corresponds to the specified instruction opcode. |
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Returns an opcode which defines the accumulator used by P Opcode. |
Find the chain of accumulator instructions in P MBB and return them in P Chain. |
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Find chains of accumulations that can be rewritten as a tree for increased ILP. |
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Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory. These values are returned as a struct ExtAddrMode which contains all relevant information to make up the address. |
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Return true if the instruction contains a base register and offset. If true, the function also sets the operand position in the instruction for the base register and offset. |
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These methods return the opcode of the frame setup/destroy instructions if they exist (‐1 otherwise). Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions. A FrameSetup MI in MF implies MFI::AdjustsStack. |
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Returns the callee operand from the given |
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Return the objective of a combiner pattern. |
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Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal. The ImmVal is a result that should be interpreted as modulo size of Reg. |
Returns true if a certain instruction is deprecated and if so returns the reason in |
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Return the current execution domain and bit mask of possible domains for instruction. |
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The limit on resource length extension we accept in MachineCombiner Pass. |
Build the equivalent inputs of a EXTRACT_SUBREG for the given |
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Fills in the necessary MachineOperands to refer to a frame index. The best way to understand this is to print |
Returns size of the frame associated with the given frame instruction. For frame setup instruction this is frame that is set up space set up after the instruction. For frame destroy instruction this is the frame freed by the caller. Note, in some cases a call frame (or a part of it) may be prepared prior to the frame setup instruction. It occurs in the calls that involve inalloca arguments. This function reports only the size of the frame part that is set up between the frame setup and destroy pseudo instructions. |
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Returns the total frame size, which is made up of the space set up inside the pair of frame start‐stop instructions and the space that is set up prior to the pair. |
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If the instruction is an increment of a constant value, return the amount. |
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Measure the specified inline asm to determine an approximation of its length. |
Build the equivalent inputs of a INSERT_SUBREG for the given |
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Sum the sizes of instructions inside of a BUNDLE, by calling |
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For BUNDLE instructions, target implementations are responsible for accounting for the size of all bundled instructions. |
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Determine whether/how the instruction size returned by getInstSizeInBytes() should be verified. |
Compute the instruction latency of a given instruction. If the instruction has higher cost when predicated, it's returned via PredCost. |
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Return the inverse operation opcode if it exists for P Opcode (e.g. add for sub and vice versa). |
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Return an index for MachineJumpTableInfo if |
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Allows targets to use appropriate copy instruction while spilitting live range of a register in register allocation. |
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Return MIR formatter to format/parse MIR operands. Target can override this virtual function and return target specific MIR formatter. |
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Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs. |
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Return true when there is potentially a faster code sequence for an instruction chain ending in |
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Return a strategy that MachineCombiner must use when creating traces. |
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Return the maximal number of alias checks on memory operands. For instructions with more than one memory operands, the alias check on a single MachineInstr pair has quadratic overhead and results in unacceptable performance in the worst case. The limit here is to clamp that maximal checks performed. Usually, that's the product of memory operand numbers from that pair of MachineInstr to be checked. For instance, with two MachineInstrs with 4 and 5 memory operands correspondingly, a total of 20 checks are required. With this limit set to 16, their alias check is skipped. We choose to limit the product instead of the individual instruction as targets may have special MachineInstrs with a considerably high number of memory operands, such as |
Get the base operand and byte offset of an instruction that reads/writes memory. This is a convenience function for callers that are only prepared to handle a single base operand. FIXME: Move Offset and OffsetIsScalable to some ElementCount‐style abstraction that supports negative offsets. |
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Get zero or more base operands and the byte offset of an instruction that reads/writes memory. Note that there may be zero base operands if the instruction accesses a constant address. It returns false if MI does not read/write memory. It returns false if base operands and offset could not be determined. It is not guaranteed to always recognize base operands and offsets in all cases. FIXME: Move Offset and OffsetIsScalable to some ElementCount‐style abstraction that supports negative offsets. |
Returns the name for the instructions with the given opcode. |
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Return the noop instruction to use for a noop. |
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Return the number of u‐operations the given machine instruction will be decoded to on the target cpu. The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources. |
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Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible. If LoadRegIndex is non‐null, it is filled in with the operand index of the operand which will hold the register holding the loaded value. |
Compute and return the use operand latency of a given pair of def and use. In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses. |
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Optional target hook which partitions |
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Returns a |
Returns how or if |
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Returns the preferred minimum clearance before an instruction with an unwanted partial register update. |
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For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references. Operands outside of the range are most likely foldable but it is not guaranteed. These instructions are unique in that stack references for some operands have the same execution cost (e.g. none) as the unfolded register forms. The ranged return is guaranteed to include all operands which can't be folded at zero cost. |
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The returned array encodes the operand index for each parameter because the operands may be commuted; the operand indices for associative operations might also be target‐specific. Each element specifies the index of {Prev, A, B, X, Y}. |
Reassociation of some instructions requires inverse operations (e.g. (X + A) ‐ Y => (X ‐ Y) + A). This method returns a pair of new opcodes (new root opcode, new prev opcode) that must be used to reassociate P Root and P Prev accoring to P Pattern. |
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Returns the opcode that should be use to reduce accumulation registers. |
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Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL. |
Build the equivalent inputs of a REG_SEQUENCE for the given |
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Returns the actual stack pointer adjustment made by an instruction as part of a call sequence. By default, only call frame setup/destroy instructions adjust the stack, but targets may want to override this to enable more fine‐grained adjustment, or adjust by a different value. |
Return an array that contains the bitmask target flag values and their names. |
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Return an array that contains the direct target flag values and their names. |
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Return an array that contains the MMO target flag values and their names. |
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Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. |
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Compute the size in bytes and offset within a stack slot of a spilled register or subregister. |
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Returns the target‐specific default value for tail duplication. This value will be used if the tail‐dup‐placement‐threshold argument is not provided. |
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Returns the target‐specific default value for tail merging. This value will be used if the tail‐merge‐size argument is not provided. |
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Return the minimum clearance before an instruction that reads an unused register. |
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Return the uniformity behavior of the given value. |
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Returns true if the target has a preference on the operands order of the given machine instruction. And specify if |
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Compute operand latency between a def of 'Reg' and a use in the current loop. Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation. |
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If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed. |
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Compute operand latency of a def of 'Reg'. Return true if the target considered it 'low'. |
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Return true when P Inst has reassociable operands in the same P MBB. |
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Return true when P Inst has reassociable sibling. |
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If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed. |
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Insert branch code into the end of the specified MachineBasicBlock. The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted. If |
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Inserts a code prefetch instruction before |
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Insert an unconditional indirect branch at the end of |
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Insert a noop into the instruction stream at the specified point. |
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Insert noops into the instruction stream at the specified point. |
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Insert a call to an outlined function into the program. Returns an iterator to the spot where we inserted the call. This must be implemented by the target. |
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Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. |
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Return true when P OpCode is an instruction which performs accumulation into one of its operand registers. |
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If the specific machine instruction is an instruction that adds an immediate value and a register, and stores the result in the given register |
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Return true if the instruction is as cheap as a move instruction. |
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Return true when P Inst is both associative and commutative. If P Invert is true, then the inverse of P Inst operation must be tested. |
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True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. This can be implemented to prevent register allocator to insert spills for |
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Return true if the instruction is a "coalescable" extension instruction. That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre‐extension value is available as a subreg of the result register. This also returns the sub‐register index in SubIdx. |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. For COPY‐instruction the method naturally returns destination and source registers as machine operands, for all other instructions the method calls target‐dependent implementation. |
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Returns true if the given |
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Given the generic extension instruction |
Returns true if the argument is a frame pseudo instruction. |
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Returns true if the argument is a frame setup pseudo instruction. |
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Return true if the function can safely be outlined from. A function |
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Return true if the function is a viable candidate for machine function splitting. The criteria for if a function can be split may vary by target. |
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Returns true if MI is an instruction we are unable to reason about (like a call or something with unmodeled side effects). |
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Return true if this opcode has high latency to its result. |
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Given |
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Return true if it's legal to split the given basic block at the specified instruction (i.e. instruction would be the start of a new basic block). |
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Check for post‐frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness. |
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Optional target hook that returns true if |
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Return true if the MachineBasicBlock can safely be split to the cold section. On AArch64, certain instructions may cause a block to be unsafe to split to the cold section. |
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Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC‐relative addressing. PC‐relative addressing modes in many CISC architectures contain (non‐PC) registers as offsets or scaling values, which inherently tags the corresponding MachineOperand with OPERAND_PCREL. |
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Return true for post‐incremented instructions. |
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Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand. |
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Returns true if the instruction is already predicated. |
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Return true if it's profitable for if‐converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if‐conversion. The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted. |
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Return true if it's profitable to unpredicate one side of a 'diamond', i.e. two sides of if‐else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1 |
Return true if the instruction would be materializable at a point in the containing function where all virtual register uses were known to be live and available in registers. |
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Return true if the input P Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, P Commuted will be set to true. |
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Return true if it's safe to move a machine instruction. This allows the backend to prevent certain special instruction sequences from being broken by instruction motion in optimization passes. By default, this returns true for every instruction. |
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Return true if it's safe to move a machine instruction that defines the specified register class. |
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Test if the given instruction should be considered a scheduling boundary. This primarily includes labels and terminators. |
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Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. Provide the identity of the two frame indices. |
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Check for post‐frame ptr elimination stack locations as well. This uses a heuristic, so it isn't reliable for correctness. |
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Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). For example, X86 may want to return true if it can fold movl (%esp), %eax subb, %al, ... Into: subb (%esp), ... |
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Determines whether |
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Return true when a code sequence can improve throughput. It should be called only for instructions in loops. |
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available. This means the only allowed uses are constants and unallocatable physical registers so that the instructions result is independent of the place in the function. |
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Returns true if MI is an unconditional tail call. |
Returns true if the instruction is a terminator instruction that has not been predicated. |
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Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl. |
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Return true for pseudo instructions that don't consume any machine resources in their current form. These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary. |
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Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction. If |
This function defines the logic to lower COPY instruction to target specific instruction(s). |
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Optional target hook to create the LLVM IR attributes for the outlined function. If overridden, the overriding function must call the default implementation. |
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See if the comparison instruction can be converted into something more efficient. E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP. |
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Try to remove the load by folding it to a register operand at the use. We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding. CopyMI returns the copy instruction possibly generated due to folding. |
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Given an instruction marked as |
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Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if‐conversion. |
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Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value. i.e. cases such as rax = shr rax, X where NullValueReg = rax. Note that if the NullValueReg is non‐zero, this function can return true even if becomes zero. Specifically cases such as NullValueReg = shl NullValueReg, 63. |
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Return true if two machine instructions would produce identical values. By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks. |
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Re‐issue the specified 'original' instruction at the specific location targeting a new destination register. The register in Orig‐>getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx. |
Attempt to reassociate P Root and P Prev according to P Pattern to reduce critical path length. |
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Reduces branches of the accumulator tree into a single register. |
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Generate code to reduce the loop iteration by one and check if the loop is finished. Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first. |
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Remove the branching code at the end of the specific MBB. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed. If |
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Replace the conditional branch in MBB with a conditional tail call. |
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Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. |
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Change the opcode of MI to execute in Domain. |
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This is an architecture‐specific helper function of reassociateOps. Set special operand attributes for new instructions after reassociation. |
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For a "cheap" instruction which doesn't enable additional sinking, should MachineSink break a critical edge to sink it anyways? |
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Returns true if the two given memory operations should be scheduled adjacent. Note that you have to add: DAG‐>addMutation(createLoadClusterDAGMutation(DAG‐>TII, DAG‐>TRI)); or DAG‐>addMutation(createStoreClusterDAGMutation(DAG‐>TII, DAG‐>TRI)); to TargetMachine::createMachineScheduler() to have an effect. |
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Return false if the instruction should not be hoisted by MachineLICM. |
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Return true if the function should be outlined from by default. |
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Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB. |
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This is a used by the pre‐regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1. |
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Return true if the instruction should be sunk by MachineSink. |
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If possible, converts the instruction to a simplified/canonical form. Returns true if the instruction was modified. |
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Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill. If |
unfoldMemoryOperand ‐ Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference. |
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Return true when a target supports MachineCombiner. |
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor. |
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Perform target‐specific instruction verification. |
Static Member Functions
Static Data Members
Protected Member Functions
Name |
Description |
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This method commutes the operands of the given machine instruction MI. The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. |
Target‐dependent implementation for foldMemoryOperand. Target‐independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at MI. |
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Target‐dependent implementation of getExtractSubregInputs. |
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Target‐dependent implementation of getInsertSubregInputs. |
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Target‐dependent implementation for getOutliningTypeImpl. |
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Target‐dependent implementation of getRegSequenceInputs. |
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Target‐dependent implementation for IsCopyInstr. If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. |
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For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually rematerializable, taking into consideration its operands. This predicate must return false if the instruction has any side effects other than producing a value. |
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Return true if the given terminator MI is not expected to spill. This sets the live interval as not spillable and adjusts phi node lowering to not introduce copies after the terminator. Use with care, these are currently used for hardware loop intrinsics in very controlled situations, created prior to registry allocation in loops that only have single phi users for the terminators value. They may run out of registers if not used carefully. |
Protected Static Member Functions
Name |
Description |
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2). One or both input values of the pair: (ResultIdx1, ResultIdx2) may be predefined to some indices or be undefined (designated by the special value 'CommuteAnyOperandIndex'). The predefined result indices cannot be re‐defined. The function returns true iff after the result pair redefinition the fixed result pair is equal to or equivalent to the source pair of indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that the pairs (x,y) and (y,x) are equivalent. |
Protected Data Members
Name |
Description |
Subtarget specific sub‐array of MCInstrInfo's RegClassByHwModeTables (i.e. the table for the active HwMode). This should be indexed by MCOperandInfo's RegClass field for LookupRegClassByHwMode operands. |
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Non-Member Functions
Name |
Description |
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering. |
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If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering. |
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