llvm::Register

Name

Description

Register [constructor]

Constructors

asMCReg

Utility to check‐convert this value to a MCRegister. The caller is expected to have already validated that this Register is, indeed, physical.

id

isPhysical

Return true if the specified register number is in the physical register namespace.

isStack

Return true if this is a stack slot.

isValid

isVirtual

Return true if the specified register number is in the virtual register namespace.

operator++

Operators to move from one register to another nearby register by adding an offset.

operator+=

Addition assignment operator

stackSlotIndex

Compute the frame index from a register value representing a stack slot.

virtRegIndex

Convert a virtual register number to a 0‐based index. The first virtual register in a function will get the index 0.

operator MCRegister

Conversion to MCRegister

operator unsigned int

Conversion to unsigned int

operator==

Equality operators

operator!=

Inequality operators

Name

Description

index2StackSlot

Convert a frame index to a stack slot register value.

index2VirtReg

Convert a 0‐based index to a virtual register number. This is the inverse operation of VirtReg2IndexFunctor below.

isPhysicalRegister

Return true if the specified register number is in the physical register namespace.

isVirtualRegister

Return true if the specified register number is in the virtual register namespace.

Name

MaxFrameIndexBitwidth

StackSlotMask

StackSlotZero

VirtualRegFlag

Name

Description

canCreatePoison

Returns true if Reg can create poison from non‐poison operands.

canCreateUndefOrPoison

Returns true if Reg can create undef or poison from non‐undef & non‐poison operands. ConsiderFlagsAndMetadata controls whether poison producing flags and metadata on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags and metadata which might be on the instruction.

canReplaceReg

Check if DstReg can be replaced with SrcReg depending on the register constraints.

constrainOperandRegClass

Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed as an argument (RegClass). If this fails, create a new virtual register in the correct class and insert a COPY before InsertPt if it is a use or after if it is a definition. In both cases, the function also updates the register of RegMo. The debug location of InsertPt is used for the new copy.

constrainOperandRegClass

Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II. If this fails, create a new virtual register in the correct class and insert a COPY before InsertPt if it is a use or after if it is a definition. In both cases, the function also updates the register of RegMo. This is equivalent to constrainOperandRegClass(..., RegClass, ...) with RegClass obtained from the MCInstrDesc. The debug location of InsertPt is used for the new copy.

constrainRegToClass

Try to constrain Reg to the specified register class. If this fails, create a new virtual register in the correct class.

extractParts

Version which handles irregular splits.

extractParts

Helper function to split a wide generic register into bitwise blocks with the given Type (which implies the number of blocks needed). The generic registers created are appended to Ops, starting at bit 0 of Reg.

extractVectorParts

Version which handles irregular sub‐vector splits.

fcmpImpliesClass

Compute the possible floating‐point classes that LHS could be based on fcmp Pred LHS, RHS.

getAnyConstantVRegValWithLookThrough

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.

getDefIgnoringCopies

Find the def instruction for Reg, folding away any trivial copies. May return nullptr if Reg is not a generic virtual register.

getDefSrcRegIgnoringCopies

Find the def instruction for Reg, and underlying value Register folding away any copies.

getFConstantSplat

Returns a floating point scalar constant of a build vector splat if it exists. When AllowUndef == true some elements can be undef but not all.

getFConstantVRegValWithLookThrough

If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns its APFloat value and def register.

getFunctionLiveInPhysReg

Return a virtual register corresponding to the incoming argument register PhysReg. This register is expected to have class RC, and optional type RegTy. This assumes all references to the register will use the same type.

getIConstantFromReg

VReg is defined by a G_CONSTANT, return the corresponding value.

getIConstantSplatSExtVal

getIConstantSplatVal

getIConstantVRegSExtVal

If VReg is defined by a G_CONSTANT fits in int64_t returns it.

getIConstantVRegVal

If VReg is defined by a G_CONSTANT, return the corresponding value.

getIConstantVRegValWithLookThrough

If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its APInt value and def register.

getOpcodeDef

See if Reg is defined by an single def instruction of type T Also try to do trivial folding if it's a COPY with same types. Returns null otherwise.

getSrcRegIgnoringCopies

Find the source register for Reg, folding away any trivial copies. It will be an output register of the instruction that getDefIgnoringCopies returns. May return an invalid register if Reg is not a generic virtual register.

isBuildVectorConstantSplat

Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.

isBuildVectorConstantSplat

Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.

isConstantOrConstantSplatVector

Determines if Def defines a constant integer or a splat vector of constant integers.

isConstantOrConstantSplatVectorFP

Determines if Def defines a float constant integer or a splat vector of float constant integers.

isGuaranteedNotToBePoison

Returns true if Reg cannot be poison, but may be undef.

isGuaranteedNotToBeUndef

Returns true if Reg cannot be undef, but may be poison.

isGuaranteedNotToBeUndefOrPoison

Returns true if Reg cannot be poison and undef.

isKnownToBeAPowerOfTwo

Test if the given value is known to have exactly one bit set. This differs from computeKnownBits in that it doesn't necessarily determine which bit is set. When OrNegative is true, the value is also considered a power of two if its negation is a power of two (i.e. its absolute value is a power of two).

isPhysRegUsedAfter

Check if physical register Reg is used after MBI.

printReg

Prints virtual and physical registers with or without a TRI instance.

printRegClassOrBank

Create Printable object to print register classes or register banks on a raw_ostream.

GISelAddressing::getPointerInfo

Returns a BaseIndexOffset which describes the pointer in Ptr.

MIPatternMatch::m_DeferredReg

Similar to m_SpecificReg/Type, but the specific value to match originated from an earlier sub‐pattern in the same mi_match expression. For example, we cannot match (add X, X) with m_GAdd(m_Reg(X), m_SpecificReg(X)) because X is not initialized at the time it's passed to m_SpecificReg. Instead, we can use m_GAdd(m_Reg(x), m_DeferredReg(X)).

MIPatternMatch::m_SpecificReg

Matches a register only if it is equal to RequestedReg.