llvm::GAnyLoad

Flags to specify different kinds of comments to output in assembly code. These flags carry semantic information not otherwise easily derivable from the IR text.

MICheckType

MIFlag

QueryType

API for querying MachineInstr properties. They are the same as MCInstrDesc queries but they are bundle aware.

Member Functions

Name

Description

operator= [deleted]

Copy assignment operator

addImplicitDefUseOperands

Add all implicit def and use operands to this instruction.

addMemOperand

Add a MachineMemOperand to the machine instruction. This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.

addOperand

addOperand overloads

addRegisterDead

We have determined MI defined a register without a use. Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

addRegisterDefined

We have determined MI defines a register. Make sure there is an operand defining Reg.

addRegisterKilled

We have determined MI kills a register. Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

allDefsAreDead

Return true if all the defs of this instruction are dead.

allImplicitDefsAreDead

Return true if all the implicit defs of this instruction are dead.

all_defs

Returns an iterator range over all operands that are (explicit or implicit) register defs.

all_uses

Returns an iterator range over all operands that are (explicit or implicit) register uses.

bundleWithPred

Bundle this instruction with its predecessor. This can be an unbundled instruction, or it can be the first instruction in a bundle.

bundleWithSucc

Bundle this instruction with its successor. This can be an unbundled instruction, or it can be the last instruction in a bundle.

canFoldAsLoad

Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant‐pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

changeDebugValuesDefReg

Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.

clearAsmPrinterFlag

Clear specific AsmPrinter flags.

clearAsmPrinterFlags

Clear the AsmPrinter bitvector.

clearFlag

clearFlag ‐ Clear a MI flag.

clearFlags

clearKillInfo

Clears kill flags on all operands.

clearRegisterDeads

Clear all dead flags on operands defining register Reg.

clearRegisterKills

Clear all kill flags affecting Reg. If RegInfo is provided, this includes all aliasing registers.

cloneInstrSymbols

Clone another MachineInstr's pre‐ and post‐ instruction symbols and replace ours with it.

cloneMemRefs

Clone another MachineInstr's memory reference descriptor list and replace ours with it.

cloneMergedMemRefs

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it.

collectDebugValues

Scan instructions immediately following MI and collect any matching DBG_VALUEs.

copyIRFlags

Copy all flags to MachineInst MIFlags

copyImplicitOps

Copy implicit register operands from specified instruction to this instruction.

debug_operands

Returns all operands that are used to determine the variable location for this DBG_VALUE instruction.

definesRegister

Return true if the MachineInstr fully defines the specified register. If TargetRegisterInfo is non‐null, then it also checks if there is a def of a super‐register. NOTE: It's ignoring subreg indices on virtual registers.

defs

Returns all explicit operands that are register definitions. Implicit definition are not included!

dropDebugNumber

Drop any variable location debugging information associated with this instruction. Use when an instruction is modified in such a way that it no longer defines the value it used to. Variable locations using that value will be dropped.

dropMemRefs

Clear this MachineInstr's memory reference descriptor list. This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.

dropPoisonGeneratingFlags

dump

dumpr

Print on dbgs() the current instruction and the instructions defining its operands and so on until we reach MaxDepth.

emitGenericError

emitInlineAsmError

Emit an error referring to the source location of this instruction. This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.

eraseFromBundle

Unlink 'this' from its basic block and delete it.

eraseFromParent

Unlink 'this' from the containing basic block and delete it.

explicit_operands

explicit_uses

findFirstPredOperandIdx

Find the index of the first operand in the operand list that is used to represent the predicate. It returns ‐1 if none is found.

findInlineAsmFlagIdx

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. Returns ‐1 if getOperand(OpIdx) does not belong to an inline asm operand group.

findRegisterDefOperand

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.

findRegisterDefOperandIdx

Returns the operand index that is a def of the specified register or ‐1 if it is not found. If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non‐null, then it also checks if there is a def of a super‐register. This may also return a register mask operand when Overlap is true.

findRegisterUseOperand

Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.

findRegisterUseOperandIdx

Returns the operand index that is a use of the specific register or ‐1 if it is not found. It further tightens the search criteria to a use that kills the register if isKill is true.

findTiedOperandIdx

Given the index of a tied register operand, find the operand it is tied to. Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.

getAlign

Return the minimum known alignment in bytes of the actual memory reference.

getAsmPrinterFlag

Return whether an AsmPrinter flag is set.

getAsmPrinterFlags

Return the asm printer flags bitvector.

getBundleSize

Return the number of instructions inside the MI bundle, excluding the bundle header.

getCFIType

Helper to extract a CFI type hash if one has been added.

getDeactivationSymbol

getDebugExpression

Return the complex address expression referenced by this DBG_VALUE instruction.

getDebugExpressionOp

Return the operand for the complex address expression referenced by this DBG_VALUE instruction.

getDebugInstrNum

getDebugInstrNum overloads

getDebugLabel

Return the debug label referenced by this DBG_LABEL instruction.

getDebugLoc

Returns the debug location id of this MachineInstr.

getDebugOffset

Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will be an invalid register if this value is not indirect, and an immediate with value 0 otherwise.

getDebugOperand

getDebugOperandIndex

getDebugOperandsForReg

Returns a range of all of the operands that correspond to a debug use of Reg.

getDebugVariable

Return the debug variable referenced by this DBG_VALUE instruction.

getDebugVariableOp

Return the operand for the debug variable referenced by this DBG_VALUE instruction.

getDesc

Returns the target instruction descriptor of this MachineInstr.

getDstReg

Get the definition register of the loaded value.

Return whether an MI flag is set.

getFlags

Return the MI flags bitvector.

getFoldedRestoreSize

Return a valid size if the instruction is a folded restore instruction.

getFoldedSpillSize

Return a valid size if the instruction is a folded spill instruction.

getHeapAllocMarker

Helper to extract a heap alloc marker if one has been added.

getInlineAsmDialect

getLocCookieMD

For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.

getMF

Return the function that contains the basic block that this instruction belongs to.

getMMO

Get the MachineMemOperand on this instruction.

getMMRAMetadata

Helper to extract mmra.op metadata.

getMemCacheHint

Returns the cache hint metadata for this load.

getMemSize

Returns the size in bytes of the memory access.

getMemSizeInBits

Returns the size in bits of the memory access.

getNextNode

Get the next node, or nullptr for the list tail.

getNumDebugOperands

Returns the total number of operands which are debug locations.

getNumDefs

Returns the total number of definitions.

getNumExplicitDefs

Returns the number of non‐implicit definitions.

getNumExplicitOperands

Returns the number of non‐implicit operands.

getNumImplicitOperands

Returns the implicit operands number.

getNumMemOperands

Return the number of memory operands.

getNumOperands

Retuns the total number of operands.

getOpcode

Returns the opcode of this MachineInstr.

getOperand

getOperandNo

Returns the number of the operand iterator I points to.

getPCSections

Helper to extract PCSections metadata target sections.

getParent

getPointerReg

Get the source register of the pointer value.

getPostInstrSymbol

Helper to extract a post‐instruction symbol if one has been added.

getPreInstrSymbol

Helper to extract a pre‐instruction symbol if one has been added.

getPrevNode

getPrevNode overloads

getRanges

Returns the Ranges that describes the dereference.

getReg

Access the Idx'th operand as a register and return it. This assumes that the Idx'th operand is a Register type.

getRegClassConstraint

Compute the static register class constraint for operand OpIdx. For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words.

getRegClassConstraintEffect

Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.

getRegClassConstraintEffectForVReg

Applies the constraints (def/use) implied by this MI on Reg to the given CurRC. If ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle.

getRestoreSize

Return a valid size if the instruction is a restore instruction.

getSpillSize

Return a valid size if the instruction is a spill instruction.

getTypeToPrint

Debugging support @{ Determine the generic type to be printed (if needed) on uses and defs.

hasComplexRegisterTies

Return true when an instruction has tied register that can't be determined by the instruction's descriptor. This is useful for MIR printing, to determine whether we need to print the ties or not.

hasDebugOperandForReg

Returns whether this debug value has at least one debug operand with the register Reg.

hasDelaySlot

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

hasExtraDefRegAllocReq

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post‐register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

hasExtraSrcRegAllocReq

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post‐register allocation passes should not attempt to change allocations for sources of instructions with this flag.

hasImplicitDef

Returns true if the instruction has implicit definition.

hasOneMemOperand

Return true if this instruction has exactly one MachineMemOperand.

hasOptionalDef

Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.

hasOrderedMemoryRef

Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. Return false if it is known to have no ordered or volatile memory references.

hasPoisonGeneratingFlags

hasPostISelHook

Return true if this instruction requires adjustment after instruction selection by calling a target hook. For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

hasProperty

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.

hasRegisterImplicitUseOperand

Returns true if the MachineInstr has an implicit‐use operand of exactly the given register (not considering sub/super‐registers).

hasUnmodeledSideEffects

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).

implicit_operands

insert

Inserts Ops BEFORE It. Can untie/retie tied operands.

isAnnotationLabel

isAsCheapAsAMove

Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., remat during two‐address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

isAtomic

Returns true if the attached MachineMemOperand has the atomic flag set.

isBarrier

Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

isBitcast

Return true if this instruction is a bitcast instruction.

isBranch

Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::analyzeBranch method can be used to get more information.

isBundle

isBundled

Return true if this instruction part of a bundle. This is true if either itself or its following instruction is marked "InsideBundle".

isBundledWithPred

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.

isBundledWithSucc

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.

isCFIInstruction

isCall

isCandidateForAdditionalCallInfo

Return true if this is a call instruction that may have an additional information associated with it.

isCommutable

Return true if this may be a 2‐ or 3‐address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

isCompare

Return true if this instruction is a comparison.

isConditionalBranch

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

isConstantValuePHI

If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return Register().

isConvergent

Return true if this instruction is convergent. Convergent instructions can not be made control‐dependent on any additional values.

isConvertibleTo3Addr

Return true if this is a 2‐address instruction which can be changed into a 3‐address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2‐address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

isCopy

isCopyLaneMask

isCopyLike

Return true if the instruction behaves like a copy. This does not include native copy instructions.

isDead

Check whether an MI is dead. If LivePhysRegs is provided, it is assumed to be at the position of MI and will be used to check the Liveness of physical register defs. If LivePhysRegs is not provided, this will pessimistically assume any PhysReg def is live. For trivially dead instructions (i.e. those without hard to model effects / wouldBeTriviallyDead), this checks deadness by analyzing defs of the MachineInstr. If the instruction wouldBeTriviallyDead, and all the defs either have dead flags or have no uses, then the instruction is said to be dead.

isDebugEntryValue

A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.

isDebugOrPseudoInstr

isDereferenceableInvariantLoad

Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function.

isEHLabel

isEHScopeReturn

Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction.

isEquivalentDbgInstr

Returns true if this instruction is a debug instruction that represents an identical debug value to Other. This function considers these debug instructions equivalent if they have identical variables, debug locations, and debug operands, and if the DIExpressions combined with the directness flags are equivalent.

isExtractSubreg

isExtractSubregLike

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1

Return true if this instruction is identical to Other. Two instructions are identical if they have the same opcode and all their operands are identical (with respect to MachineOperand::isIdenticalTo()). Note that this means liveness related flags (dead, undef, kill) do not affect the notion of identical.

isIdentityCopy

Return true is the instruction is an identity copy.

isImplicitDef

isIndirectBranch

Return true if this is an indirect branch, such as a branch through a register.

isIndirectDebugValue

A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate.

isInlineAsm

isInsertSubreg

isInsertSubregLike

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)

isInsideBundle

Return true if MI is in a bundle (but not the first MI in a bundle).

isJumpTableDebugInfo

isKill

isLabel

Returns true if the MachineInstr represents a label.

isLifetimeMarker

isLoadFoldBarrier

Returns true if it is illegal to fold a load across this instruction.

isMetaInstruction

Return true if this instruction doesn't produce any output in the form of executable instructions.

isMoveImmediate

Return true if this instruction is a move immediate (including conditional moves) instruction.

isMoveReg

Return true if this instruction is a register move. (including moving values from subreg to reg)

isNonListDebugValue

isNotDuplicable

Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

isOperandSubregIdx

Return true if operand OpIdx is a subregister index.

isPHI

isPosition

isPreISelOpcode

Return true if this is an instruction that should go through the usual legalization steps.

isPredicable

Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

isPseudo

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

isPseudoProbe

isRegSequence

isRegSequenceLike

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.

isRegTiedToDefOperand

Return true if the use operand of the specified index is tied to a def operand. It also returns the def operand index by reference if DefOpIdx is not null.

isRegTiedToUseOperand

Given the index of a register def operand, check if the register def is tied to a source operand, due to either two‐address elimination or inline assembly constraints. Returns the first tied use operand index by reference if UseOpIdx is not null.

isRematerializable

Returns true if this instruction is a candidate for remat. This flag is deprecated, please don't use it anymore. If this flag is set, the isReMaterializableImpl() method is called to verify the instruction is really rematerializable.

isReturn

isSafeToMove

Return true if it is safe to move this instruction. If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.

isSelect

Return true if this instruction is a select instruction.

isSimple

Returns true if the memory operation is neither atomic or volatile.

isStackAligningInlineAsm

isSubregToReg

isTerminator

Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions.

isTransient

Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy‐like instructions), or if this instruction doesn't have an execution‐time cost.

isUnconditionalBranch

Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

isUndefDebugValue

Return true if the instruction is a debug value which describes a part of a variable as unavailable.

isUnordered

Returns true if this memory operation doesn't have any ordering constraints other than normal aliasing. Volatile and (ordered) atomic memory operations can't be reordered.

isVariadic

Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

isVolatile

Returns true if the attached MachineMemOpeand as the volatile flag set.

killsRegister

Return true if the MachineInstr kills the specified register. If TargetRegisterInfo is non‐null, then it also checks if there is a kill of a super‐register.

mayAlias

Assumes any physical registers used to compute addresses have the same value for both instructions. Returns false if neither instruction writes to memory.

mayFoldInlineAsmRegOp

Returns true if the register operand can be folded with a load or store into a frame index. Does so by checking the InlineAsm::Flag immediate operand at OpId ‐ 1.

mayLoad

Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

mayLoadOrStore

Return true if this instruction could possibly read or modify memory.

mayRaiseFPException

Return true if this instruction could possibly raise a floating‐point exception. This is the case if the instruction is a floating‐point instruction that can in principle raise an exception, as indicated by the MCID::MayRaiseFPException property, and at the same time, the instruction is used in a context where we expect floating‐point exceptions are not disabled, as indicated by the NoFPExcept MI flag.

mayStore

Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

memoperands

Access to memory operands of the instruction. If there are none, that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.

memoperands_begin

Access to memory operands of the instruction.

memoperands_empty

Return true if we don't have any memory operands which described the memory access done by this instruction. If this is true, calling code must be conservative.

memoperands_end

Access to memory operands of the instruction.

mergeFlagsWith

Return the MIFlags which represent both MachineInstrs. This should be used when merging two MachineInstrs into one. This routine does not modify the MIFlags of this MachineInstr.

modifiesRegister

Return true if the MachineInstr modifies (fully define or partially define) the specified register. NOTE: It's ignoring subreg indices on virtual registers.

moveBefore

Move the instruction before MovePos.

Examine the instruction number of this MachineInstr. May be zero if it hasn't been assigned a number yet.

print

Print this MI to OS. Don't print information that can be inferred from other instructions if IsStandalone is false. It is usually true when only a fragment of the function is printed. Only print the defs and the opcode if SkipOpers is true. Otherwise, also print operands if SkipDebugLoc is true. Otherwise, also print the debug loc, with a terminating newline. TII is used to print the opcode name. If it's not present, but the MI is in a function, the opcode will be printed using the function's TII.

readsRegister

Return true if the MachineInstr reads the specified register. If TargetRegisterInfo is non‐null, then it also checks if there is a read of a super‐register. This does not count partial redefines of virtual registers as reads: %reg1024:6 = OP.

readsVirtualRegister

Return true if the MachineInstr reads the specified virtual register. Take into account that a partial define is a read‐modify‐write operation.

readsWritesVirtualRegister

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. This also considers partial defines. If Ops is not null, all operand indices for Reg are added.

registerDefIsDead

Returns true if the register is dead in this machine instruction. If TargetRegisterInfo is non‐null, then it also checks if there is a dead def of a super‐register.

removeFromBundle

Unlink this instruction from its basic block and return it without deleting it.

removeFromParent

Unlink 'this' from the containing basic block, and return it without deleting it.

removeOperand

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

removePHIIncomingValueFor

Remove all incoming values of Phi instruction for the given block.

setAsmPrinterFlag

Set a flag for the AsmPrinter.

setCFIType

Set the CFI type for the instruction.

setDeactivationSymbol

setDebugInstrNum

Set instruction number of this MachineInstr. Avoid using unless you're deserializing this information.

setDebugLoc

Replace current source information with new such. Avoid using this, the constructor argument is preferable.

setDebugValueUndef

Sets all register debug operands in this debug value instruction to be undef.

setDesc

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

setFlag

Set a MI flag.

setFlags

setHeapAllocMarker

Set a marker on instructions that denotes where we should create and emit heap alloc site labels. This waits until after instruction selection and optimizations to create the label, so it should still work if the instruction is removed or duplicated.

setMMRAMetadata

setMemRefs

Assign this MachineInstr's memory reference descriptor list.

setPCSections

setPhysRegsDeadExcept

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

setPostInstrSymbol

Set a symbol that will be emitted just after the instruction itself.

setPreInstrSymbol

Set a symbol that will be emitted just prior to the instruction itself.

setRegisterDefReadUndef

Mark all subregister defs of register Reg with the undef flag. This function is used when we determined to have a subregister def in an otherwise undefined super register.

shouldUpdateAdditionalCallInfo

Return true if copying, moving, or erasing this instruction requires updating additional call info (see copyCallInfo, moveCallInfo, eraseCallInfo).

substituteRegister

Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.

tieOperands

Add a tie between the register operands at DefIdx and UseIdx. The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.

unbundleFromPred

Break bundle above this instruction.

unbundleFromSucc

Break bundle below this instruction.

untieRegOperand

Break any tie involving OpIdx.

uses

Returns all operands which may be register uses. This may include unrelated operands which are not register uses.

usesCustomInsertionHook

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

wouldBeTriviallyDead

Return true if this instruction would be trivially dead if all of its defined registers were dead.

Static Member Functions

Name

classof

copyFlagsFromInstruction

Non-Member Functions

Name

Description

AnalyzePhysRegInBundle

AnalyzePhysRegInBundle ‐ Analyze how the current instruction or bundle uses a physical register. This function should not be called after operator++(), it expects a fresh iterator.

AnalyzeVirtRegInBundle

AnalyzeVirtRegInBundle ‐ Analyze how the current instruction or bundle uses a virtual register. This function should not be called after operator++(), it expects a fresh iterator.

AnalyzeVirtRegLanesInBundle

Return a pair of lane masks (reads, writes) indicating which lanes this instruction uses with Reg.

canLowerMemCpyFamily

Matcher for memcpy‐like instructions. For non‐zero lengths, MemOps contains the load/store types to emit.

constrainSelectedInstRegOperands

Mutate the newly‐selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class. This could involve inserting COPYs before (for uses) or after (for defs). This requires the number of operands to match the instruction description.

getIConstantSplatSExtVal

getIConstantSplatVal

getSplatIndex

getVectorSplat

Examples:

isAllOnesOrAllOnesSplat

Return true if the value is a constant ‐1 integer or a splatted vector of a constant ‐1 integer (with no undefs if AllowUndefs is false).

isAssertMI

Returns true if the instruction MI is one of the assert instructions.

isBuildVectorAllOnes

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.

isBuildVectorAllZeros

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.

isBuildVectorConstantSplat

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.

isBuildVectorConstantSplat

Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the elements are SplatValue or undef.

isConstantOrConstantVector

Return true if the specified instruction is known to be a constant, or a vector of constants.

isConstantOrConstantVector

Determines if MI defines a constant integer or a build vector of constant integers. Treats undef values as constants.

isNullOrNullSplat

Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with no undefs if AllowUndefs is false). This will handle G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC as truncation is not an issue for null values.

isTriviallyDead

Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have other side effects.

phys_regs_and_masks

Returns an iterator range over all physical register and mask operands for MI and bundled instructions. This also skips any debug operands.

updateDbgValueForSpill

Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when modifying an instruction in place while iterating over a basic block.

GISelAddressing::aliasIsKnownForLoadStore

Compute whether or not a memory access at MI1 aliases with an access at MI2

GISelAddressing::instMayAlias

Returns true if the instruction MI may alias Other. This function uses multiple strategies to detect aliasing, whereas aliasIsKnownForLoadStore just looks at the addresses of load/stores and is tries to reason about base/index/offsets.

Derived Classes

Name

Description

GExtLoad

Represents either a G_SEXTLOAD, G_ZEXTLOAD, or G_FPEXTLOAD.

GFPExtLoad

Represents a G_FPEXTLOAD.

GLoad

Represents a G_LOAD.

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