[#llvm-SelectionDAGISel]
= xref:llvm.adoc[llvm]::SelectionDAGISel
:relfileprefix: ../
:mrdocs:

SelectionDAGISel ‐ This is the common base class used for SelectionDAG‐based pattern‐matching instruction selectors.

== Synopsis

Declared in `<llvm/CodeGen/SelectionDAGISel.h>`

[source,cpp,subs="verbatim,replacements,macros,-callouts"]
----
class SelectionDAGISel;
----

== Enums

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/_04enum.adoc[`Unnamed enum`] 
| Flags describing chain/glue/variadic shape for EmitNode / MorphNodeTo.
| xref:llvm/SelectionDAGISel/BuiltinOpcodes.adoc[`BuiltinOpcodes`] 
| Opcodes used by the TableGen‐generated DAG matcher state machine.
|===


== Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/2constructor.adoc[`SelectionDAGISel`]         [.small]#[constructor]#
| Construct a SelectionDAG instruction selector for target machine `tm.`
| xref:llvm/SelectionDAGISel/2destructor.adoc[`~SelectionDAGISel`] [.small]#[destructor]# [.small]#[virtual]#
| Destroy the SelectionDAG instruction selector.
| xref:llvm/SelectionDAGISel/CheckAndMask.adoc[`CheckAndMask`] 
| Return true if AND of `LHS` with `RHS` matches desired mask `DesiredMaskS.`
| xref:llvm/SelectionDAGISel/CheckComplexPattern.adoc[`CheckComplexPattern`]  [.small]#[virtual]#
| Match complex pattern `PatternNo` rooted at `N` and append results.
| xref:llvm/SelectionDAGISel/CheckNodePredicate.adoc[`CheckNodePredicate`]  [.small]#[virtual]#
| Run TableGen node predicate `PredNo` on `Op` and return whether it succeeds.
| xref:llvm/SelectionDAGISel/CheckNodePredicateWithOperands.adoc[`CheckNodePredicateWithOperands`]  [.small]#[virtual]#
| Run TableGen node predicate `PredNo` on `Op` with recorded `Operands.`
| xref:llvm/SelectionDAGISel/CheckOrMask.adoc[`CheckOrMask`] 
| Return true if OR of `LHS` with `RHS` matches desired mask `DesiredMaskS.`
| xref:llvm/SelectionDAGISel/CheckPatternPredicate.adoc[`CheckPatternPredicate`]  [.small]#[virtual]#
| Run TableGen pattern predicate `PredNo` and return whether it succeeds.
| xref:llvm/SelectionDAGISel/ComplexPatternFuncMutatesDAG.adoc[`ComplexPatternFuncMutatesDAG`]  [.small]#[virtual]#
| Return true if complex patterns for this target can mutate the DAG.
| xref:llvm/SelectionDAGISel/IsProfitableToFold.adoc[`IsProfitableToFold`]  [.small]#[virtual]#
| Return true if folding operand `N` of `U` into `Root` is profitable.
| xref:llvm/SelectionDAGISel/PostprocessISelDAG.adoc[`PostprocessISelDAG`]  [.small]#[virtual]#
| PostprocessISelDAG() ‐ This hook allows the target to hack on the graph right after selection.
| xref:llvm/SelectionDAGISel/PreprocessISelDAG.adoc[`PreprocessISelDAG`]  [.small]#[virtual]#
| PreprocessISelDAG ‐ This hook allows targets to hack on the graph before instruction selection starts.
| xref:llvm/SelectionDAGISel/RunSDNodeXForm.adoc[`RunSDNodeXForm`]  [.small]#[virtual]#
| Apply TableGen SDNodeXForm `XFormNo` to value `V.`
| xref:llvm/SelectionDAGISel/Select.adoc[`Select`]  [.small]#[virtual]#
| Main hook for targets to transform nodes into machine nodes.
| xref:llvm/SelectionDAGISel/SelectCodeCommon.adoc[`SelectCodeCommon`] 
| Interpret TableGen matcher bytecode and select `NodeToMatch.`
| xref:llvm/SelectionDAGISel/SelectInlineAsmMemoryOperand.adoc[`SelectInlineAsmMemoryOperand`]  [.small]#[virtual]#
| Select `Op` as a target memory addressing mode for inline asm.
| xref:llvm/SelectionDAGISel/emitFunctionEntryCode.adoc[`emitFunctionEntryCode`]  [.small]#[virtual]#
| Emit target‐specific code at function entry before selection.
| xref:llvm/SelectionDAGISel/getBatchAA.adoc[`getBatchAA`] 
| Returns a (possibly null) pointer to the current BatchAAResults.
| xref:llvm/SelectionDAGISel/getTargetLowering.adoc[`getTargetLowering`] 
| Return the target lowering interface used by this selector.
| xref:llvm/SelectionDAGISel/getValueTypeForHwMode.adoc[`getValueTypeForHwMode`]  [.small]#[virtual]#
| Return the MVT for TableGen type index `Index` under the current HwMode.
| xref:llvm/SelectionDAGISel/initializeAnalysisResults-05.adoc[`initializeAnalysisResults`] 
| `initializeAnalysisResults` overloads
| xref:llvm/SelectionDAGISel/isOrEquivalentToAdd.adoc[`isOrEquivalentToAdd`] 
| Return true if OR node `N` is equivalent to an ADD of a stack offset.
| xref:llvm/SelectionDAGISel/mayRaiseFPException.adoc[`mayRaiseFPException`] 
| Return whether the node may raise an FP exception.
| xref:llvm/SelectionDAGISel/runOnMachineFunction.adoc[`runOnMachineFunction`]  [.small]#[virtual]#
| Run SelectionDAG instruction selection on machine function `mf.`
|===


== Static Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/EnforceNodeIdInvariant.adoc[`EnforceNodeIdInvariant`] 
| Propagate node‐ID invalidation through users of newly created node `N.`
| xref:llvm/SelectionDAGISel/InvalidateNodeId.adoc[`InvalidateNodeId`] 
| Mark node IDs invalid for topological pruning after replacing `N.`
| xref:llvm/SelectionDAGISel/IsLegalToFold.adoc[`IsLegalToFold`] 
| Return true if operand `N` of `U` may legally fold into `Root.`
| xref:llvm/SelectionDAGISel/getNumFixedFromVariadicInfo.adoc[`getNumFixedFromVariadicInfo`] 
| Return how many fixed arity values to skip when copying from a variadic root.
| xref:llvm/SelectionDAGISel/getUninvalidatedNodeId.adoc[`getUninvalidatedNodeId`] 
| Return the original node ID of `N` before InvalidateNodeId negation.
|===


== Data Members

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/AC.adoc[`AC`] 
| Assumption cache for the current function, if available.
| xref:llvm/SelectionDAGISel/BatchAA.adoc[`BatchAA`] 
| Optional batch alias‐analysis results for the current function.
| xref:llvm/SelectionDAGISel/CurDAG.adoc[`CurDAG`] 
| SelectionDAG being built and selected for the current function.
| xref:llvm/SelectionDAGISel/ElidedArgCopyInstrs.adoc[`ElidedArgCopyInstrs`] 
| Instructions whose argument copies were elided during selection.
| xref:llvm/SelectionDAGISel/FastISelFailed.adoc[`FastISelFailed`] 
| True if FastISel was attempted and failed for the current function.
| xref:llvm/SelectionDAGISel/FuncInfo.adoc[`FuncInfo`] 
| Per‐function lowering state shared with the DAG builder.
| xref:llvm/SelectionDAGISel/FuncName.adoc[`FuncName`] 
| Name of the function currently being instruction‐selected.
| xref:llvm/SelectionDAGISel/GFI.adoc[`GFI`] 
| GC function info for the current function, if any.
| xref:llvm/SelectionDAGISel/HwMode.adoc[`HwMode`] 
| Hardware mode used by getValueTypeForHwMode for the current subtarget.
| xref:llvm/SelectionDAGISel/LibInfo.adoc[`LibInfo`] 
| Target library information for the current function.
| xref:llvm/SelectionDAGISel/LibcallLowering.adoc[`LibcallLowering`] 
| Libcall lowering information for the current target.
| xref:llvm/SelectionDAGISel/MF.adoc[`MF`] 
| Machine function currently being instruction‐selected.
| xref:llvm/SelectionDAGISel/MMI.adoc[`MMI`] 
| Module‐level machine information for the current module.
| xref:llvm/SelectionDAGISel/MatchFilterFuncName.adoc[`MatchFilterFuncName`] 
| True if the current function matches `‐filter‐print‐funcs`.
| xref:llvm/SelectionDAGISel/ORE.adoc[`ORE`] 
| Current optimization remark emitter. Used to report things like combines and FastISel failures.
| xref:llvm/SelectionDAGISel/OptLevel.adoc[`OptLevel`] 
| Optimization level used for instruction selection.
| xref:llvm/SelectionDAGISel/RegInfo.adoc[`RegInfo`] 
| Register information for the current machine function.
| xref:llvm/SelectionDAGISel/SDB.adoc[`SDB`] 
| Builder that lowers IR into the current SelectionDAG.
| xref:llvm/SelectionDAGISel/SP.adoc[`SP`] 
| Stack‐protector layout info for the current function, if any.
| xref:llvm/SelectionDAGISel/SwiftError.adoc[`SwiftError`] 
| Tracker for Swift error values during ISel.
| xref:llvm/SelectionDAGISel/TII.adoc[`TII`] 
| Target instruction information for the current subtarget.
| xref:llvm/SelectionDAGISel/TLI.adoc[`TLI`] 
| Target lowering interface for the current subtarget.
| xref:llvm/SelectionDAGISel/TM.adoc[`TM`] 
| Target machine for the current compilation.
| xref:llvm/SelectionDAGISel/TTI.adoc[`TTI`] 
| Target transform info for the current function, if available.
|===


== Protected Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/ReplaceNode.adoc[`ReplaceNode`] 
| Replace all uses of `F` with `T,` then remove `F` from the DAG.
| xref:llvm/SelectionDAGISel/ReplaceUses-09.adoc[`ReplaceUses`] 
| `ReplaceUses` overloads
| xref:llvm/SelectionDAGISel/SelectInlineAsmMemoryOperands.adoc[`SelectInlineAsmMemoryOperands`] 
| Select memory operands of an INLINEASM node, rewriting `Ops` in place.
| xref:llvm/SelectionDAGISel/getIncludePathForIndex.adoc[`getIncludePathForIndex`]  [.small]#[virtual]#
| Return the TableGen include path for pattern instantiation index `index.`
| xref:llvm/SelectionDAGISel/getPatternForIndex.adoc[`getPatternForIndex`]  [.small]#[virtual]#
| Return the TableGen pattern text for matcher coverage index `index.`
| xref:llvm/SelectionDAGISel/shouldOptForSize.adoc[`shouldOptForSize`] 
| Return true if the current function should be optimized for code size.
|===


== Protected Data Members

[cols="1,4"]
|===
| Name| Description
| xref:llvm/SelectionDAGISel/DAGSize.adoc[`DAGSize`] 
| DAGSize ‐ Size of DAG being instruction selected.
|===


== Non-Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/createBURRListDAGScheduler.adoc[`createBURRListDAGScheduler`]
| Create a bottom‐up register usage reduction list scheduler.
| xref:llvm/createDAGLinearizer.adoc[`createDAGLinearizer`]
| Create a no‐scheduling scheduler that linearizes the DAG topologically.
| xref:llvm/createDefaultScheduler.adoc[`createDefaultScheduler`]
| Create an instruction scheduler appropriate for the target.
| xref:llvm/createFastDAGScheduler.adoc[`createFastDAGScheduler`]
| Create a fast SelectionDAG instruction scheduler.
| xref:llvm/createHybridListDAGScheduler.adoc[`createHybridListDAGScheduler`]
| Create a bottom‐up register‐pressure‐aware list scheduler that uses latency.
| xref:llvm/createILPListDAGScheduler.adoc[`createILPListDAGScheduler`]
| Create a bottom‐up register‐pressure‐aware list scheduler that favors ILP.
| xref:llvm/createSourceListDAGScheduler.adoc[`createSourceListDAGScheduler`]
| Create a bottom‐up list scheduler that prefers source code order.
| xref:llvm/createVLIWDAGScheduler.adoc[`createVLIWDAGScheduler`]
| Create a top‐down DFA‐driven list scheduler for VLIW targets.
|===


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