[#llvm-ScheduleDAGMI]
= xref:llvm.adoc[llvm]::ScheduleDAGMI
:relfileprefix: ../
:mrdocs:

ScheduleDAG that schedules according to a MachineSchedStrategy.

== Synopsis

Declared in `<llvm/CodeGen/MachineScheduler.h>`

[source,cpp,subs="verbatim,replacements,macros,-callouts"]
----
class ScheduleDAGMI
    : public xref:llvm/ScheduleDAGInstrs.adoc[ScheduleDAGInstrs]
----

== Description

This is the common functionality between PreRA and PostRA MachineScheduler. It simply schedules machine instructions according to the given strategy without much extra book‐keeping.

== Base Classes

[cols="1,4"]
|===
| Name| Description
| `xref:llvm/ScheduleDAGInstrs.adoc[ScheduleDAGInstrs]`
| A ScheduleDAG for scheduling lists of MachineInstr.
|===

== Type Aliases

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGInstrs/SUList.adoc[`SUList`] 
| List of SUnits associated with a memory value during DAG construction.
|===


== Enums

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGInstrs/DumpDirection.adoc[`DumpDirection`] 
| The direction that should be used to dump the scheduled Sequence.
|===


== Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGMI/2constructor.adoc[`ScheduleDAGMI`]         [.small]#[constructor]#
| Construct a DAG scheduler for context `C` using strategy `S.`
| xref:llvm/ScheduleDAGMI/2destructor.adoc[`~ScheduleDAGMI`] [.small]#[destructor]# [.small]#[virtual]#
| Destroy the schedule DAG and owned strategy.
| xref:llvm/ScheduleDAG/operator_assign.adoc[`operator=`]  [.small]#[deleted]#
| Copy assignment is deleted; ScheduleDAG is passed by reference only.
| xref:llvm/ScheduleDAGInstrs/IsReachable.adoc[`IsReachable`] 
| IsReachable ‐ Checks if SU is reachable from TargetSU.
| xref:llvm/ScheduleDAG/VerifyScheduledDAG.adoc[`VerifyScheduledDAG`] 
| Verifies that all SUnits were scheduled and that their state is consistent. Returns the number of scheduled SUnits.
| xref:llvm/ScheduleDAG/addCustomGraphFeatures.adoc[`addCustomGraphFeatures`]  [.small]#[virtual]#
| Adds custom features for a visualization of the ScheduleDAG.
| xref:llvm/ScheduleDAGInstrs/addEdge.adoc[`addEdge`] 
| Add a DAG edge to the given SU with the given predecessor dependence data.
| xref:llvm/ScheduleDAGMI/addMutation.adoc[`addMutation`] 
| Add a postprocessing step to the DAG builder.
| xref:llvm/ScheduleDAGInstrs/addSchedBarrierDeps.adoc[`addSchedBarrierDeps`] 
| Adds dependencies from region instructions to the scheduling barrier.
| xref:llvm/ScheduleDAGInstrs/begin.adoc[`begin`] 
| Returns an iterator to the top of the current scheduling region.
| xref:llvm/ScheduleDAGMI/bottom.adoc[`bottom`] 
| Return an iterator to the bottom of the unscheduled zone.
| xref:llvm/ScheduleDAGInstrs/buildSchedGraph.adoc[`buildSchedGraph`] 
| Builds SUnits for the current scheduling region.
| xref:llvm/ScheduleDAGInstrs/canAddEdge.adoc[`canAddEdge`] 
| True if an edge can be added from PredSU to SuccSU without creating a cycle.
| xref:llvm/ScheduleDAG/clearDAG.adoc[`clearDAG`] 
| Clears the DAG state (between regions).
| xref:llvm/ScheduleDAGMI/doMBBSchedRegionsTopDown.adoc[`doMBBSchedRegionsTopDown`]  [.small]#[virtual]#
| Return true to process MBB scheduling regions top‐down.
| xref:llvm/ScheduleDAGInstrs/dump.adoc[`dump`]  [.small]#[virtual]#
| Dumps the scheduling DAG for debugging.
| xref:llvm/ScheduleDAGInstrs/dumpNode.adoc[`dumpNode`]  [.small]#[virtual]#
| Dumps a single scheduling unit for debugging.
| xref:llvm/ScheduleDAG/dumpNodeName.adoc[`dumpNodeName`] 
| Dump the printable name of `SU.`
| xref:llvm/ScheduleDAGInstrs/end.adoc[`end`] 
| Returns an iterator to the bottom of the current scheduling region.
| xref:llvm/ScheduleDAGMI/enterRegion.adoc[`enterRegion`]  [.small]#[virtual]#
| Prepare the next scheduling region within a basic block.
| xref:llvm/ScheduleDAGInstrs/exitRegion.adoc[`exitRegion`]  [.small]#[virtual]#
| Called when the scheduler has finished scheduling the current region.
| xref:llvm/ScheduleDAGInstrs/finalizeSchedule.adoc[`finalizeSchedule`]  [.small]#[virtual]#
| Allow targets to perform final scheduling actions at the level of the whole MachineFunction. By default does nothing.
| xref:llvm/ScheduleDAGMI/finishBlock.adoc[`finishBlock`]  [.small]#[virtual]#
| Finish scheduling for the current basic block.
| xref:llvm/ScheduleDAGInstrs/fixupKills.adoc[`fixupKills`] 
| Fixes register kill flags that scheduling has made invalid.
| xref:llvm/ScheduleDAGInstrs/getCluster.adoc[`getCluster`] 
| Get the specific cluster, return nullptr for InvalidClusterId.
| xref:llvm/ScheduleDAGInstrs/getClusters.adoc[`getClusters`] 
| Returns the array of the clusters.
| xref:llvm/ScheduleDAGInstrs/getDAGName.adoc[`getDAGName`]  [.small]#[virtual]#
| Returns a label for the region of code covered by the DAG.
| xref:llvm/ScheduleDAGInstrs/getGraphNodeLabel.adoc[`getGraphNodeLabel`]  [.small]#[virtual]#
| Returns a label for a DAG node that points to an instruction.
| xref:llvm/ScheduleDAG/getInstrDesc.adoc[`getInstrDesc`] 
| Returns the MCInstrDesc of this SUnit. Returns NULL for SDNodes without a machine opcode.
| xref:llvm/ScheduleDAGMI/getLIS.adoc[`getLIS`] 
| Return the LiveIntervals instance for use in DAG mutators and such.
| xref:llvm/ScheduleDAGInstrs/getSUnit.adoc[`getSUnit`] 
| Returns an existing SUnit for this MI, or nullptr.
| xref:llvm/ScheduleDAGInstrs/getSchedClass.adoc[`getSchedClass`] 
| Resolves and cache a resolved scheduling class for an SUnit.
| xref:llvm/ScheduleDAGInstrs/getSchedModel.adoc[`getSchedModel`] 
| Gets the machine model for instruction scheduling.
| xref:llvm/ScheduleDAGMI/hasVRegLiveness.adoc[`hasVRegLiveness`]  [.small]#[virtual]#
| Return true if this DAG supports VReg liveness and RegPressure.
| xref:llvm/ScheduleDAGMI/moveInstruction.adoc[`moveInstruction`] 
| Change the position of an instruction within the basic block and update live ranges and region boundary iterators.
| xref:llvm/ScheduleDAGInstrs/newSUnit.adoc[`newSUnit`] 
| Creates a new SUnit and return a ptr to it.
| xref:llvm/ScheduleDAGMI/schedule.adoc[`schedule`]  [.small]#[virtual]#
| Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
| xref:llvm/ScheduleDAGInstrs/setDumpDirection.adoc[`setDumpDirection`] 
| Sets the direction used when dumping the scheduled sequence.
| xref:llvm/ScheduleDAGInstrs/shouldScheduleSingleMIRegions.adoc[`shouldScheduleSingleMIRegions`] 
| Whether regions with a single MI should be scheduled.
| xref:llvm/ScheduleDAGMI/startBlock.adoc[`startBlock`]  [.small]#[virtual]#
| Begin scheduling within basic block `bb.`
| xref:llvm/ScheduleDAGMI/top.adoc[`top`] 
| Return an iterator to the top of the unscheduled zone.
| xref:llvm/ScheduleDAGMI/viewGraph-08.adoc[`viewGraph`] 
| `viewGraph` overloads
|===


== Data Members

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAG/EntrySU.adoc[`EntrySU`] 
| Special node for the region entry.
| xref:llvm/ScheduleDAG/ExitSU.adoc[`ExitSU`] 
| Special node for the region exit.
| xref:llvm/ScheduleDAG/MF.adoc[`MF`] 
| Machine function
| xref:llvm/ScheduleDAG/MRI.adoc[`MRI`] 
| Virtual/real register map
| xref:llvm/ScheduleDAG/SUnits.adoc[`SUnits`] 
| The scheduling units.
| xref:llvm/ScheduleDAG/StressSched.adoc[`StressSched`] 
| When true, stress‐test the scheduler.
| xref:llvm/ScheduleDAG/TII.adoc[`TII`] 
| Target instruction information
| xref:llvm/ScheduleDAG/TM.adoc[`TM`] 
| Target processor
| xref:llvm/ScheduleDAG/TRI.adoc[`TRI`] 
| Target processor register info
|===


== Protected Types

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGInstrs/Value2SUsMap.adoc[`Value2SUsMap`] 
| A map from ValueType to SUList, used during DAG construction, as a means of remembering which SUs depend on which memory locations.
|===


== Protected Type Aliases

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGInstrs/DbgValueVector.adoc[`DbgValueVector`] 
| Pairs of DBG_VALUE instructions and the instructions they follow.
|===


== Protected Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGInstrs/addBarrierChain.adoc[`addBarrierChain`] 
| Adds barrier‐chain edges from all SUs in `map,` then clears the map.
| xref:llvm/ScheduleDAGInstrs/addChainDependencies-0e.adoc[`addChainDependencies`] 
| `addChainDependencies` overloads
| xref:llvm/ScheduleDAGInstrs/addChainDependency.adoc[`addChainDependency`] 
| Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency.
| xref:llvm/ScheduleDAGInstrs/addPhysRegDataDeps.adoc[`addPhysRegDataDeps`] 
| Adds data dependencies for the physical‐register operand at `OperIdx.`
| xref:llvm/ScheduleDAGInstrs/addPhysRegDeps.adoc[`addPhysRegDeps`] 
| Adds all physical‐register dependencies for the operand at `OperIdx.`
| xref:llvm/ScheduleDAGInstrs/addVRegDefDeps.adoc[`addVRegDefDeps`] 
| Adds virtual‐register definition dependencies for the operand at `OperIdx.`
| xref:llvm/ScheduleDAGInstrs/addVRegUseDeps.adoc[`addVRegUseDeps`] 
| Adds virtual‐register use dependencies for the operand at `OperIdx.`
| xref:llvm/ScheduleDAGMI/checkSchedLimit.adoc[`checkSchedLimit`] 
| Return false if the misched‐cutoff limit has been reached.
| xref:llvm/ScheduleDAGInstrs/deadDefHasNoUse.adoc[`deadDefHasNoUse`] 
| Returns true if the def register in `MO` has no uses.
| xref:llvm/ScheduleDAG/dumpNodeAll.adoc[`dumpNodeAll`] 
| Dump `SU` and all of its scheduling attributes.
| xref:llvm/ScheduleDAGMI/dumpSchedule.adoc[`dumpSchedule`] 
| dump the scheduled Sequence.
| xref:llvm/ScheduleDAGMI/dumpScheduleTraceBottomUp.adoc[`dumpScheduleTraceBottomUp`] 
| Print an execution trace of the schedule bottom‐up.
| xref:llvm/ScheduleDAGMI/dumpScheduleTraceTopDown.adoc[`dumpScheduleTraceTopDown`] 
| Print execution trace of the schedule top‐down or bottom‐up.
| xref:llvm/ScheduleDAGMI/findRootsAndBiasEdges.adoc[`findRootsAndBiasEdges`] 
| Find top/bottom roots and bias weak edges before queue setup.
| xref:llvm/ScheduleDAGInstrs/getAAForDep.adoc[`getAAForDep`] 
| Returns a (possibly null) pointer to the current BatchAAResults.
| xref:llvm/ScheduleDAGInstrs/getLaneMaskForMO.adoc[`getLaneMaskForMO`] 
| Returns a mask for which lanes get read/written by the given (register) machine operand.
| xref:llvm/ScheduleDAGMI/initQueues.adoc[`initQueues`] 
| Release ExitSU predecessors and setup scheduler queues.
| xref:llvm/ScheduleDAGInstrs/initSUnits.adoc[`initSUnits`] 
| Creates an SUnit for each instruction in the current region.
| xref:llvm/ScheduleDAGMI/placeDebugValues.adoc[`placeDebugValues`] 
| Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
| xref:llvm/ScheduleDAGMI/postProcessDAG.adoc[`postProcessDAG`] 
| Apply each ScheduleDAGMutation step in order. This allows different instances of ScheduleDAGMI to perform custom DAG postprocessing.
| xref:llvm/ScheduleDAGMI/releasePred.adoc[`releasePred`] 
| Release predecessor edge `PredEdge` of `SU` after scheduling.
| xref:llvm/ScheduleDAGMI/releasePredecessors.adoc[`releasePredecessors`] 
| Release all predecessors of `SU` after it is scheduled.
| xref:llvm/ScheduleDAGMI/releaseSucc.adoc[`releaseSucc`] 
| Release successor edge `SuccEdge` of `SU` after scheduling.
| xref:llvm/ScheduleDAGMI/releaseSuccessors.adoc[`releaseSuccessors`] 
| Release all successors of `SU` after it is scheduled.
| xref:llvm/ScheduleDAGMI/updateQueues.adoc[`updateQueues`] 
| Update scheduler DAG and queues after scheduling an instruction.
|===


== Protected Data Members

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGMI/AA.adoc[`AA`] 
| Alias analysis used while building memory dependencies.
| xref:llvm/ScheduleDAGInstrs/AAForDep.adoc[`AAForDep`] 
| Optional batch alias‐analysis results used while adding memory deps.
| xref:llvm/ScheduleDAGInstrs/BB.adoc[`BB`] 
| The block in which to insert instructions
| xref:llvm/ScheduleDAGInstrs/BarrierChain.adoc[`BarrierChain`] 
| Generic side‐effecting instruction that acts as a scheduling barrier.
| xref:llvm/ScheduleDAGInstrs/CanHandleTerminators.adoc[`CanHandleTerminators`] 
| True if this scheduler can safely include terminators as DAG nodes.
| xref:llvm/ScheduleDAGInstrs/Clusters.adoc[`Clusters`] 
| Clusters of related SUnits discovered while building the DAG.
| xref:llvm/ScheduleDAGMI/CurrentBottom.adoc[`CurrentBottom`] 
| The bottom of the unscheduled zone.
| xref:llvm/ScheduleDAGMI/CurrentTop.adoc[`CurrentTop`] 
| The top of the unscheduled zone.
| xref:llvm/ScheduleDAGInstrs/CurrentVRegDefs.adoc[`CurrentVRegDefs`] 
| Tracks the last instruction(s) in this region defining each virtual register. There may be multiple current definitions for a register with disjunct lanemasks.
| xref:llvm/ScheduleDAGInstrs/CurrentVRegUses.adoc[`CurrentVRegUses`] 
| Tracks the last instructions in this region using each virtual register.
| xref:llvm/ScheduleDAGInstrs/DbgValues.adoc[`DbgValues`] 
| Remember instruction that precedes DBG_VALUE. These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.
| xref:llvm/ScheduleDAGInstrs/Defs.adoc[`Defs`] 
| Map from register units to SUnits that define them in the current walk.
| xref:llvm/ScheduleDAGInstrs/DumpDir.adoc[`DumpDir`] 
| Direction used when dumping the schedule.
| xref:llvm/ScheduleDAGInstrs/FirstDbgValue.adoc[`FirstDbgValue`] 
| First DBG_VALUE instruction preceding the scheduled region, if any.
| xref:llvm/ScheduleDAGMI/LIS.adoc[`LIS`] 
| Live intervals used by DAG mutations and pressure tracking.
| xref:llvm/ScheduleDAGInstrs/LiveRegs.adoc[`LiveRegs`] 
| Set of live physical registers for updating kill flags.
| xref:llvm/ScheduleDAGMI/MBFI.adoc[`MBFI`] 
| Block frequencies used by scheduling heuristics.
| xref:llvm/ScheduleDAGInstrs/MFI.adoc[`MFI`] 
| Frame information for the function.
| xref:llvm/ScheduleDAGInstrs/MISUnitMap.adoc[`MISUnitMap`] 
| After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.
| xref:llvm/ScheduleDAGInstrs/MLI.adoc[`MLI`] 
| Loop information for the function.
| xref:llvm/ScheduleDAGInstrs/MemOpsProcessed.adoc[`MemOpsProcessed`] 
| Number of memory operations processed while building the DAG.
| xref:llvm/ScheduleDAGMI/Mutations.adoc[`Mutations`] 
| Ordered list of DAG postprocessing steps.
| xref:llvm/ScheduleDAGInstrs/NumRegionInstrs.adoc[`NumRegionInstrs`] 
| Instructions in this region (distance(RegionBegin, RegionEnd)).
| xref:llvm/ScheduleDAGInstrs/RegionBegin.adoc[`RegionBegin`] 
| The beginning of the range to be scheduled.
| xref:llvm/ScheduleDAGInstrs/RegionEnd.adoc[`RegionEnd`] 
| The end of the range to be scheduled.
| xref:llvm/ScheduleDAGInstrs/RemoveKillFlags.adoc[`RemoveKillFlags`] 
| True if the DAG builder should remove kill flags (in preparation for rescheduling).
| xref:llvm/ScheduleDAGMI/SchedImpl.adoc[`SchedImpl`] 
| Strategy that selects the next node to schedule.
| xref:llvm/ScheduleDAGInstrs/SchedModel.adoc[`SchedModel`] 
| TargetSchedModel provides an interface to the machine model.
| xref:llvm/ScheduleDAGInstrs/ScheduleSingleMIRegions.adoc[`ScheduleSingleMIRegions`] 
| True if regions with a single MI should be scheduled.
| xref:llvm/ScheduleDAGInstrs/Topo.adoc[`Topo`] 
| Topo ‐ A topological ordering for SUnits which permits fast IsReachable and similar queries.
| xref:llvm/ScheduleDAGInstrs/TrackLaneMasks.adoc[`TrackLaneMasks`] 
| Whether lane masks should get tracked.
| xref:llvm/ScheduleDAGInstrs/UnknownValue.adoc[`UnknownValue`] 
| For an unanalyzable memory access, this Value is used in maps.
| xref:llvm/ScheduleDAGInstrs/Uses.adoc[`Uses`] 
| Map from register units to SUnits that use them in the current walk.
|===


== Non-Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/createSchedPostRA.adoc[`createSchedPostRA`]
| Create a generic scheduler with no vreg liveness or DAG mutation passes.
| xref:llvm/fuseInstructionPair.adoc[`fuseInstructionPair`]
| Fuse two scheduling units so they are scheduled back to back.
|===

== Derived Classes

[cols="1,4"]
|===
| Name| Description
| xref:llvm/ScheduleDAGMILive.adoc[`ScheduleDAGMILive`] 
| ScheduleDAG that tracks live intervals and register pressure.
|===


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