[#llvm-MCInstrDesc]
= xref:llvm.adoc[llvm]::MCInstrDesc
:relfileprefix: ../
:mrdocs:

Describe properties of one target instruction class.

== Synopsis

Declared in `<llvm/MC/MCInstrDesc.h>`

[source,cpp,subs="verbatim,replacements,macros,-callouts"]
----
class MCInstrDesc;
----

== Description

This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.

== Member Functions

[cols="1,4"]
|===
| Name| Description
| xref:llvm/MCInstrDesc/canFoldAsLoad.adoc[`canFoldAsLoad`] 
| Return true if this instruction can be folded as a memory operand.
| xref:llvm/MCInstrDesc/findFirstPredOperandIdx.adoc[`findFirstPredOperandIdx`] 
| Find the index of the first operand in the operand list that is used to represent the predicate. It returns ‐1 if none is found.
| xref:llvm/MCInstrDesc/getFlags.adoc[`getFlags`] 
| Return flags of this instruction.
| xref:llvm/MCInstrDesc/getNumDefs.adoc[`getNumDefs`] 
| Return the number of MachineOperands that are register definitions.
| xref:llvm/MCInstrDesc/getNumOperands.adoc[`getNumOperands`] 
| Return the number of declared MachineOperands for this instruction.
| xref:llvm/MCInstrDesc/getOpcode.adoc[`getOpcode`] 
| Return the opcode number for this descriptor.
| xref:llvm/MCInstrDesc/getOperandConstraint.adoc[`getOperandConstraint`] 
| Returns the value of the specified operand constraint if it is present. Returns ‐1 if it is not present.
| xref:llvm/MCInstrDesc/getSchedClass.adoc[`getSchedClass`] 
| Return the scheduling class index for this instruction.
| xref:llvm/MCInstrDesc/getSize.adoc[`getSize`] 
| Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode.
| xref:llvm/MCInstrDesc/hasDefOfPhysReg.adoc[`hasDefOfPhysReg`] 
| Return true if this instruction defines the specified physical register, either explicitly or implicitly.
| xref:llvm/MCInstrDesc/hasDelaySlot.adoc[`hasDelaySlot`] 
| Returns true if the specified instruction has a delay slot which must be filled by the code generator.
| xref:llvm/MCInstrDesc/hasExplicitDefOfPhysReg.adoc[`hasExplicitDefOfPhysReg`] 
| Return true if this instruction explicitly defines the specified physical register.
| xref:llvm/MCInstrDesc/hasExtraDefRegAllocReq.adoc[`hasExtraDefRegAllocReq`] 
| Return true if defs have extra register‐allocation constraints.
| xref:llvm/MCInstrDesc/hasExtraSrcRegAllocReq.adoc[`hasExtraSrcRegAllocReq`] 
| Return true if sources have extra register‐allocation constraints.
| xref:llvm/MCInstrDesc/hasImplicitDefOfPhysReg.adoc[`hasImplicitDefOfPhysReg`] 
| Return true if this instruction implicitly defines the specified physical register.
| xref:llvm/MCInstrDesc/hasImplicitUseOfPhysReg.adoc[`hasImplicitUseOfPhysReg`] 
| Return true if this instruction implicitly uses the specified physical register.
| xref:llvm/MCInstrDesc/hasOptionalDef.adoc[`hasOptionalDef`] 
| Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.
| xref:llvm/MCInstrDesc/hasPostISelHook.adoc[`hasPostISelHook`] 
| Return true if this instruction needs post‐ISel adjustment.
| xref:llvm/MCInstrDesc/hasUnmodeledSideEffects.adoc[`hasUnmodeledSideEffects`] 
| Return true if this instruction has side effects that are not modeled by other flags. This does not return true for instructions whose effects are captured by:
| xref:llvm/MCInstrDesc/implicit_defs.adoc[`implicit_defs`] 
| Return registers potentially written by any instance of this instruction.
| xref:llvm/MCInstrDesc/implicit_uses.adoc[`implicit_uses`] 
| Return registers potentially read by any instance of this instruction.
| xref:llvm/MCInstrDesc/isAdd.adoc[`isAdd`] 
| Return true if the instruction is an add instruction.
| xref:llvm/MCInstrDesc/isAsCheapAsAMove.adoc[`isAsCheapAsAMove`] 
| Return true if this instruction costs no more than a move.
| xref:llvm/MCInstrDesc/isAuthenticated.adoc[`isAuthenticated`] 
| Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx from ARMv8.3, which perform loads/branches with authentication).
| xref:llvm/MCInstrDesc/isBarrier.adoc[`isBarrier`] 
| Return true if this instruction stops control flow from falling through.
| xref:llvm/MCInstrDesc/isBitcast.adoc[`isBitcast`] 
| Return true if this instruction is a bitcast instruction.
| xref:llvm/MCInstrDesc/isBranch.adoc[`isBranch`] 
| Return true if this is a conditional, unconditional, or indirect branch.
| xref:llvm/MCInstrDesc/isCall.adoc[`isCall`] 
| Return true if the instruction is a call.
| xref:llvm/MCInstrDesc/isCommutable.adoc[`isCommutable`] 
| Return true if this may be a commutable 2‐ or 3‐address instruction.
| xref:llvm/MCInstrDesc/isCompare.adoc[`isCompare`] 
| Return true if this instruction is a comparison.
| xref:llvm/MCInstrDesc/isConditionalBranch.adoc[`isConditionalBranch`] 
| Return true if this is a conditional branch that may fall through.
| xref:llvm/MCInstrDesc/isConvergent.adoc[`isConvergent`] 
| Return true if this instruction is convergent.
| xref:llvm/MCInstrDesc/isConvertibleTo3Addr.adoc[`isConvertibleTo3Addr`] 
| Return true if this 2‐address instruction can become 3‐address.
| xref:llvm/MCInstrDesc/isExtractSubregLike.adoc[`isExtractSubregLike`] 
| Return true if this instruction behaves like EXTRACT_SUBREG.
| xref:llvm/MCInstrDesc/isIndirectBranch.adoc[`isIndirectBranch`] 
| Return true if this is an indirect branch, such as a branch through a register.
| xref:llvm/MCInstrDesc/isInsertSubregLike.adoc[`isInsertSubregLike`] 
| Return true if this instruction behaves like INSERT_SUBREG.
| xref:llvm/MCInstrDesc/isMetaInstruction.adoc[`isMetaInstruction`] 
| Return true if this is a meta instruction that doesn't produce any output in the form of executable instructions.
| xref:llvm/MCInstrDesc/isMoveImmediate.adoc[`isMoveImmediate`] 
| Return true if this instruction is a move immediate (including conditional moves) instruction.
| xref:llvm/MCInstrDesc/isMoveReg.adoc[`isMoveReg`] 
| Return true if the instruction is a register to register move.
| xref:llvm/MCInstrDesc/isNotDuplicable.adoc[`isNotDuplicable`] 
| Return true if this instruction cannot be safely duplicated.
| xref:llvm/MCInstrDesc/isPreISelOpcode.adoc[`isPreISelOpcode`] 
| Return true if this is a pre‐ISel opcode.
| xref:llvm/MCInstrDesc/isPredicable.adoc[`isPredicable`] 
| Return true if this instruction has a predicate operand.
| xref:llvm/MCInstrDesc/isPseudo.adoc[`isPseudo`] 
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
| xref:llvm/MCInstrDesc/isRegSequenceLike.adoc[`isRegSequenceLike`] 
| Return true if this instruction behaves like REG_SEQUENCE.
| xref:llvm/MCInstrDesc/isRematerializable.adoc[`isRematerializable`] 
| Returns true if this instruction is a candidate for remat. This flag is only used in TargetInstrInfo method isTriviallyRematerializable.
| xref:llvm/MCInstrDesc/isReturn.adoc[`isReturn`] 
| Return true if the instruction is a return.
| xref:llvm/MCInstrDesc/isSelect.adoc[`isSelect`] 
| Return true if this is a select instruction.
| xref:llvm/MCInstrDesc/isTerminator.adoc[`isTerminator`] 
| Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions.
| xref:llvm/MCInstrDesc/isTrap.adoc[`isTrap`] 
| Return true if this instruction is a trap.
| xref:llvm/MCInstrDesc/isUnconditionalBranch.adoc[`isUnconditionalBranch`] 
| Return true if this is an unconditional branch.
| xref:llvm/MCInstrDesc/isVariadic.adoc[`isVariadic`] 
| Return true if this instruction can have a variable number of operands.
| xref:llvm/MCInstrDesc/mayAffectControlFlow.adoc[`mayAffectControlFlow`] 
| Return true if this instruction may affect control flow.
| xref:llvm/MCInstrDesc/mayLoad.adoc[`mayLoad`] 
| Return true if this instruction could possibly read memory.
| xref:llvm/MCInstrDesc/mayRaiseFPException.adoc[`mayRaiseFPException`] 
| Return true if this instruction may raise a floating‐point exception.
| xref:llvm/MCInstrDesc/mayStore.adoc[`mayStore`] 
| Return true if this instruction could possibly modify memory.
| xref:llvm/MCInstrDesc/operands.adoc[`operands`] 
| Return the declared operand info for this instruction.
| xref:llvm/MCInstrDesc/usesCustomInsertionHook.adoc[`usesCustomInsertionHook`] 
| Return true if this instruction needs custom DAG insertion.
| xref:llvm/MCInstrDesc/variadicOpsAreDefs.adoc[`variadicOpsAreDefs`] 
| Return true if variadic operands of this instruction are definitions.
|===


== Data Members

[cols="1,4"]
|===
| Name| Description
| xref:llvm/MCInstrDesc/Flags.adoc[`Flags`] 
| Bitmask of MCID::Flag values describing instruction properties.
| xref:llvm/MCInstrDesc/ImplicitOffset.adoc[`ImplicitOffset`] 
| Offset to the start of the implicit operand list.
| xref:llvm/MCInstrDesc/NumDefs.adoc[`NumDefs`] 
| Number of operands that are definitions.
| xref:llvm/MCInstrDesc/NumImplicitDefs.adoc[`NumImplicitDefs`] 
| Number of registers implicitly defined.
| xref:llvm/MCInstrDesc/NumImplicitUses.adoc[`NumImplicitUses`] 
| Number of registers implicitly used.
| xref:llvm/MCInstrDesc/NumOperands.adoc[`NumOperands`] 
| Number of declared operands (may be more if variable_ops).
| xref:llvm/MCInstrDesc/OpInfoOffset.adoc[`OpInfoOffset`] 
| Offset to info about operands.
| xref:llvm/MCInstrDesc/Opcode.adoc[`Opcode`] 
| The opcode number.
| xref:llvm/MCInstrDesc/SchedClass.adoc[`SchedClass`] 
| Enum identifying the instruction scheduling class.
| xref:llvm/MCInstrDesc/Size.adoc[`Size`] 
| Number of bytes in encoding.
| xref:llvm/MCInstrDesc/TSFlags.adoc[`TSFlags`] 
| Target‐specific flag values.
|===



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