llvm::MCSubtargetInfo

Name

Description

HwModeType

Identify which kind of hardware‐mode ID to retrieve from a subtarget.

Name

Description

MCSubtargetInfo [constructor]

Constructors

~MCSubtargetInfo [destructor] [virtual]

Destroy the subtarget info.

operator=

Assignment operators

ApplyFeatureFlag

Apply a feature flag and return the re‐computed feature bits, including all feature bits implied by the flag.

ClearFeatureBitsTransitively

Clear feature bits and all other bits they imply.

SetFeatureBitsTransitively

Set/clear additional feature bits, including all other bits they imply.

ToggleFeature

ToggleFeature overloads

checkFeatureExpression

Check whether the current subtarget satisfies a target feature expression.

checkFeatures

Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.

enableWritePrefetching [virtual]

Return true if prefetching should also be done for writes.

getAllProcessorDescriptions

Return processor descriptions.

getAllProcessorFeatures

Return processor features.

getCPU

Return the CPU name being targeted.

getCacheAssociativity [virtual]

Return the cache associatvity for the given level of cache. Level is zero‐based, so a value of zero means the first level of cache.

getCacheLineSize

getCacheLineSize overloads

getCacheSize [virtual]

Return the cache size in bytes for the given level of cache. Level is zero‐based, so a value of zero means the first level of cache.

getEnabledProcessorFeatures

Return the list of processor features currently enabled.

getFeatureBits

Return the feature bitset for the current CPU and feature string.

getFeatureString

Return the feature string used to configure this subtarget.

getHwMode [virtual]

Return the HwMode ID for the requested type from this subtarget.

getHwModeSet [virtual]

Return a bit set containing all HwMode IDs of the current subtarget.

getInstrItineraryForCPU

Get scheduling itinerary of a CPU.

getMaxPrefetchIterationsAhead [virtual]

Return the maximum prefetch distance in terms of loop iterations.

getMinPrefetchStride [virtual]

Return the minimum stride necessary to trigger software prefetching.

getPrefetchDistance [virtual]

Return the preferred prefetch distance in terms of instructions.

getReadAdvanceCycles

Return the read‐advance cycle count for a use of SC.

getReadAdvanceEntries

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

getSchedModel

Get the machine model for this subtarget's CPU.

getSchedModelForCPU

Get the machine model of a CPU.

getTargetTriple

Return the target triple for this subtarget.

getTuneCPU

Return the CPU name being tuned for.

getWriteLatencyEntry

Return the write‐latency entry for definition DefIdx of SC.

getWriteProcResBegin

Return an iterator at the first process resource consumed by the given scheduling class.

getWriteProcResEnd

Return an iterator one past the last process resource for SC.

hasFeature

Return true if feature Feature is enabled.

initInstrItins

Initialize an InstrItineraryData instance.

isCPUStringValid

Check whether the CPU string is valid.

resolveCPU

Look up the processor entry for a CPU name, resolving aliases. Returns nullptr if the name matches neither a processor nor an alias.

resolveVariantSchedClass [virtual]

Resolve a variant scheduling class for the given MCInst and CPU.

setDefaultFeatures

Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.

setFeatureBits

Replace the current feature bitset.

shouldPrefetchAddressSpace [virtual]

Return true if the target wants to issue a prefetch in address space AS.

Name

Description

InitMCProcessorInfo

Initialize the scheduling model and feature bits.

Name

Description

createCustomBehaviour

Create a default CustomBehaviour for llvm‐mca.

createInstrPostProcess

Create a default InstrPostProcess for llvm‐mca.

createInstrumentManager

Create a default InstrumentManager for llvm‐mca.

Name

Description

TargetSubtargetInfo

Generic base class for all target‐specific subtarget information.